Abstract: A method for optimizing routing mesh segment widths within limits imposed by voltage drop and metal migration requirements, beginning with an initial mesh comprising a plurality of horizontal segments forming rows and a plurality of vertical segments forming columns. First, a voltage drop and current density associated with each segment is determined. Then a first width for each segment is found by scaling each segment width using a voltage drop scaling factor so that the routing mesh has a maximum voltage drop that satisfies the voltage drop requirement. Next, widths for each segment are determined such that the metal migration requirement minus a margin is satisfied. Then the method ensures that each segment within each row, and each segment within each column, is not more than a first scaling factor wider than its neighboring segments.

Abstract: A method of planarizing a first side of a semiconductor wafer with a polishing system includes the step of polishing the first side of the wafer in order to remove material from the wafer. The method also includes the step of moving a lens of a confocal optical system between a number of lens positions so as to maintain focus on the first side of the wafer during the polishing step. The method further includes the step of determining a rate-of-movement value based on movement of the lens during the moving step. Moreover, the method includes the step of stopping the polishing step if the rate-of-movement value has a predetermined relationship with a movement threshold value. An apparatus for polishing a first side of a semiconductor wafer is also disclosed.

Abstract: A mask is provided which has a complex transmission function and which includes a transparent layer and a non-transparent layer. The transparent layer has three types of phase-shifting elements, each imparting a different phase shift relative to the others, with the phase-shifting elements alternating in both x and y dimensions. The non-transparent layer has holes arranged in an approximately equally spaced grid pattern defined by common points in borders of the phase-shifting elements. Centers of at least two holes in the non-transparent layer have different offsets from their corresponding common points. Also provided is a mask blank which includes a transparent layer and a non-transparent layer. The transparent layer has three types of phase-shifting elements, each imparting a different phase shift relative to the others, with the phase-shifting elements alternating in both x and y dimensions.

Abstract: The present invention provides for a shielded capacitor in a digital CMOS fabrication process. The shield capacitor comprises a first surface (also known as a top plate) and a second surface (the bottom plate). The bottom plate has two portions which are connected, and the two portions of the bottom plate are positioned to sandwich the top plate in between the portions. A polysilicon layer is fabricated between the plates and the substrate of the semiconductor to isolate the plates from the substrate. To build the shielded capacitor, the polysilicon layer is fabricated first, then the plates are built on top of the polysilicon layer. The polysilicon layer is silicized and is often connected to the ground.

Abstract: A capacitor network has an uncomplicated construction enabling the capacitance of the capacitor network to be easily increased or decreased. The capacitor network has a plurality of component capacitors formed from two metallic foil layers on opposite sides of a printed circuit board interconnected by lines disposed on both sides of said printed circuit board. The component capacitors of the capacitor network are arranged into at least one series circuit section and at least one parallel circuit section. The series circuit section includes two or more component capacitor, each including at least one component capacitor, connected in series. The parallel circuit section includes two or more parallel-connected component capacitor circuits, each including at least one component capacitor.

Abstract: An optical disk controller reads CD-ROM disks at high speeds that commonly produce errors. Errors in the headers that identify sectors are tolerated by the sector-search hardware. The disk-controller firmware writes a virtual target register the previous sector's header's minutes, seconds, frame (MSF), which is one less that the desired sector's MSF, or MSF-1. A physical target that precedes the virtual target is searched for. The physical target precedes the desired sector by N sectors, so that the physical target is MSF-N. When the physical target matches a header read from the disk, a good sector found flag is set. The physical target is then incremented for each new sector and compared to the virtual target. Once the physical target matches the virtual target, the following sector is buffered to the host. The raw header from the disk is stored and error corrections are made using the error correction byte following the sector's data.

Abstract: High voltage and low voltage devices are provided on a common semiconductor substrate. An integrated semiconductor circuit includes a semiconductor substrate of a first conductivity type. Well regions of a first conductivity type and well regions of a second conductivity type are formed in the substrate. Low voltage devices are formed in well regions of the first conductivity type. A high voltage device includes source/drain regions of the second conductivity type formed, respectively, in well regions of the second conductivity type, an oxide region disposed on a surface of the substrate located above a region of the substrate that serves as a channel for the high voltage device, and a gate region disposed on the oxide region.

Abstract: A demodulator for digital-versatile disk (DVD) optical disks converts 16-bit codewords stored on the disk into 8-bit symbols or user bytes that are sent to the host after error correction. Rather than use the modulation tables in the DVD specification in reverse, the entries in the modulation table are sorted and combined. The four states stored in the DVD modulation table are reduced to two states or conditions. All entries from states 1 and 4 are sorted into unique tables that have unique mappings of codewords to symbols. Since the unique mappings are not sequence or state dependent, no state information is stored in the unique tables. Entries from states 2 and 3 are sorted into duplicates tables that have duplicate mappings, where a codeword can map to two different symbols, depending on the state sequence. One of the two symbols is chosen based on bits in the following codeword, which is the next state.

Abstract: A programmable audio/video encoder capable of receiving an encoding algorithm from an external digital information source. In one embodiment, the system accepts recordable DVD disks having a read-only sector for storing customized video encoding algorithms and programs the programmable video encoder with the customized video encoding algorithms prior to encoding and recording a video signal on the disk. By designing the video encoding algorithms to optimize one or more of a number of desirable attributes, the DVD media vendors can then create “classes” of recordable DVD disks, i.e. high capacity, high quality, high speed, high image detail, high color resolution, variable frame rate, etc. One programmable video encoder for this embodiment would include an instruction memory for storing the customized video algorithms, a video buffer for buffering the video signal, and a CPU which encodes the video signal according to the customized video algorithms.

Abstract: Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the pins of the cells. Because of the large number of the cells and the complex connections required, it is essential that wire routine be done correctly to avoid any congestion of wires. Congestion of wires can be determined by actually routing of the wires to connect the cells; however, the routing process is computationally expensive. For determination of congestion, the only required information are the location of the connections, or edges, to connect the pins of the IC. The present invention discloses a method to quickly provide a good estimate of the location of the edges, or connections for an IC. The present invention provides for a method to determine all the edges and superedges (bounding boxes, or areas where an edge will take space) of an IC without requiring to determine the actual routing of the wires of an IC.

Abstract: Clock generating circuitry comprises a first frequency multiplier for multiplying the frequency of a reference clock applied thereto by 2n, where n is a natural integer, and for furnishing the frequency-multiplied clock, a frequency divider for dividing the frequency of the frequency-multiplied clock furnished by the first frequency multiplier by 227, and for furnishing the frequency-divided clock, and a second frequency multiplier for multiplying the frequency of the frequency-divided clock from the frequency divider by 128, and for furnishing the frequency-multiplied clock. The reference clock can have a frequency of about 4.43 MHz.

Abstract: An optical disk system is presented which stores index information allowing playback of selected portions of a presentation recorded upon an optical disk, along with an associated method. The index information includes navigation data indicating the physical location of a beginning of a selected portion of a presentation stored upon the optical disk. One embodiment of the optical disk system includes a memory unit operably coupled to a disk drive unit and an input device. The disk drive unit retrieves identification data, encoded video data, and navigation data stored upon an optical disk (e.g., a DVD). The encoded video data may be, for example, a recorded presentation such as a movie. The input device produces an output signal in response to user input, wherein the output signal indicates a beginning of a selected portion of the encoded video data. The memory unit includes a non-volatile portion for storing the identification data and the index information.

Abstract: A circuit and method is provided for initiating an exception routine using exception information stored within architectured registers. Exception information is generated in response to a memory access exception caused by a speculative load instruction for loading a first register data from memory. The exception information, once generated, is stored within a first register. Thereafter, an instruction for operating on data stored in a second register is received and decoded. In response, the second register is checked to determine whether the second register contained exception information. If the second register contains exception information, then an exception routine is initiated. If, however, a second register does not contain exception information, then the instruction is executed and data within the second register is used in the execution.

Abstract: A method for assigning signals to specific metal layers through the use of interconnect wire load models that are metal layer dependent. The method allows synthesis and layout tools to route signal wires on select metal layers at an early stage in the design process. A technology library for use in designing integrated circuits is provided. In addition to traditional library components such as logic gate information, the technology library includes routing wire load models that are metal layer dependent. The wire load information reflects the electrical properties of signal wires formed on different metal layers, and provides more accurate timing estimates than generic wire delay values. The additional information influences the delay calculations of the synthesis process in such a way that the delay a signal encounters on a specific metal layer can be approximated very closely. Of significance to the present invention, a wire-metal layer attribute file is compiled by the synthesis process.

Abstract: A bridge translates addresses between a first bus and a second bus, with a larger address space capability. The bridge stores “high address” information and combines that information with address information from a device on the first bus when the device desires to transfer information from the first bus to the second bus. The bridge accesses high address information using information identifying the device.

Abstract: A control system in a data storage apparatus and associated methods for attempting to accommodate the vibrations resulting from rotating a data storage medium. The control system comprises a neural network which utilizes detected vibrations resulting from the rotation of data storage media to learn the characteristics of the rotational imbalance of rotating data storage media. Thereafter, the rotation of a data storage medium and/or movement of a data head is controlled based on the characteristics learned.

Abstract: Process monitoring circuitry according to the invention incorporates test structures placed across an integrated circuit die to monitor the performance of the fabrication process across the die. The integrity of the semiconductor fabrication process used to manufacture a particular integrated circuit is ascertained by comparing data extracted the test structures by automated test equipment (ATE) to simulation values. In one embodiment in the invention, the process monitoring circuitry comprises inverters arranged in a generally linear fashion. The inverters may be composed of simple CMOS inverters or other logic gates configured as inverters. The logic gates are arranged in horizontal and/or vertical test paths in which the gates are disposed across various sections of the integrated circuit die. An input test pad and an output test pad for each test path are provided at opposing sides of the integrated circuit die.

Abstract: According to the present invention, bitlines may be precharged to the supply voltage (Vdd) less a multiple of the transistor threshold voltage (Vtn), where the multiple is greater than or equal to 2. By precharging to a lower voltage, power consumption is reduced and memory speed is increased.

Abstract: In a 100BASE-T4 protocol network, the “carrier_status” signal associated with an incoming packet on a PMA of a given port of a Clause 27 repeater is obviated and a direct connection between PMAs and a Clause 27 repeater in the network is eliminated by transmitting synthetic preamble signals over the PMA-Repeater Data Interface to the Clause 27 repeater corresponding to the given port at an early time prior to the time that the actual preamble information of the packet is transmitted over that data interface. Receipt of the synthetic preamble signals causes the repeater to awaken and to repeat the synthetic preamble signals to other ports of the repeater. In turn, the other ports become quiet in anticipation of data to be repeated from the given port to the other ports of the repeater.

Abstract: In a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together, a channel region has a triple structure. Thus, a high electric field is formed in a corner portion between the step side region and the second surface region and in the vicinity thereof. A high electric field is also formed in the first surface region. As a result, the efficiency, with which electrons are injected into a floating gate, is considerably increased.