Abstract: A method and apparatus for transferring data from a host to a node through a fabric connecting the host to the node. A chip architecture is provided in which a protocol engine provides for on ship processing in transferring data such that frequent interrupts from various components within the chip may be processed without intervention from the host processor. Additionally, context managers are provided to transmit and receive data. The protocol engine creates a list of transmit activities, which is traversed by the context managers, which in turn execute the listed activity in a fashion independent from the protocol engine. In receiving data, the context managers provide a mechanism to process frames of data originating from various sources without requiring intervention from the protocol engine. When receiving data, the context managers are able to process frames from different sources, which arrive out of order.

Abstract: In a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together, a channel region has a triple structure. Thus, a high electric field is formed in a corner portion between the step side region and the second surface region and in the vicinity thereof. A high electric field is also formed in the first surface region. As a result, the efficiency, with which electrons are injected into a floating gate, is considerably increased.

Abstract: A low impact buffer structure disposed in unused silicon area in a signal line routing channel between logic cell rows of an integrated circuit. In a buffer cell according to the invention, power to the buffer is provided by the power supply rails of one or more nearby logic cell rows. Both the connections to the supply rails and the connections between the transistors of the buffer cell are constructed of a polysilicon material and/or lower metal layer. In this manner, the buffer cell does not significantly impact the routing of metal signal lines in the signal line routing channel. In addition, the buffer cells can be arranged in a “staggered” configuration wherein separate buffers are provided in individual routing tracks of a signal line routing channel, further reducing the possibility of interference with normal signal routing.

Abstract: Lifetime of a short-channel NMOS device is increased by modifying distributions of electrically active LDD dopant at boundaries of the device's LDD regions. The LDD dopant distributions are modified by implanting counter-dopants at the boundaries of the LDD regions. Group III counter-dopants such as boron and group IV elements such as silicon alter activation properties of the LDD dopant. The dopant distributions are modified at the device's n-junctions to reduce the maximum electric field displacement at an interface defined by the device's gate and substrate. The dopant distributions can be further modified to shape the n-junctions such that hot carriers are injected away from the gate.

Abstract: Methods and apparatus for planarizing the surface of a semiconductor wafer by applying non-uniform pressure distributions across the back side of the wafer are disclosed. According to one aspect of the present invention, a chemical mechanical polishing apparatus for polishing a first surface of a semiconductor wafer includes a polishing pad which polishes the first surface of the semiconductor wafer. The apparatus also includes a first mechanism which is used to hold, or otherwise support, the wafer during polishing, and a second mechanism that is used to apply a non-uniform pressure distribution through the first mechanism, directly onto a second surface of the wafer. The second mechanism is further used to facilitate polishing the first surface of the semiconductor wafer such that the first surface of the semiconductor wafer is evenly polished.

Abstract: An integrated circuit oscillator input cell has an oscillator input pad, an oscillator feedback pad, a core terminal, an inverter and an electrostatic discharge protection circuit. The inverter has an inverter input, which is coupled to the oscillator input pad, and an inverter output, which is coupled to the oscillator feedback pad and the core terminal. The electrostatic discharge protection circuit includes a plurality of N-channel protection transistors, which are coupled to the oscillator input pad. The N-channel protection transistors are the only protection transistors that are coupled to the oscillator input pad.

Abstract: A software test case client/server system provides selective access to a central repository of test case data used in testing a software program. A test case server stores and manages test case data in a central repository. A test client communicates between a test program and the test server to identify tests case data, and versions of such data, with desired read/write status required in testing a software program. A test program automates selection of test case data, software program test execution, and verification of software program results. In an exemplary embodiment, symbolic links and copies of test case data are recorded in a destination directory structure accessible by a software program under test. In an alternate embodiment, a revision control system (RCS) is used to access the central repository and provide copies of selected test case data in a destination directory structure accessible by a software program under test.

Abstract: A self-timing circuit with bit cell leakage current compensation provides a worst-case delay for a sense application read of a memory core. The self-timing memory circuit includes a worst-case dummy bit cell, a column of leakage current simulating dummy bit cells, and a dummy sense amplifier. The worst-case dummy bit cell is occupied to a dummy word line and a dummy bit line and is configured to drive the dummy bit line or dummy bit line pair to a first differential state when the dummy word line is asserted. The column of leakage current simulating dummy bit cells are coupled to the dummy tit line and are configured to delay the driving of the dummy bit line to the first differential state due to leakage current between the leakage current simulating dummy bit cells and the dummy bit line or bit line pair.

Abstract: Routing layers are assigned to connection segments in integrated circuit design. A routing description that includes connection segments and a vertex where at least two of the connection segments connect to each other is obtained. A penalty is determined for the vertex based on a potential layer assignment combination for the connection segments that connect at the vertex, and routing layers are assigned to the connection segments based on the determined penalty.

Abstract: Two implementations of the inverse wavelet transform for use in an image decompression system do not waste computation power on the zero-valued values inserted into the data stream during an upsampling process. The implementation optimized for low-bandwidth applications toggles between even and odd modes each clock cycle. In even/odd mode, the transformed values are multiplied by the even/odd filter coefficients. The implementation optimized for high-bandwidth applications multiplies the transformed values by the even and odd filter coefficients seperately in two sets of multipliers and outputs two different results each clock cycle.

Abstract: A dynamic random access memory (DRAM) segment incorporates at least one shielding conductor spaced from a matrix of memory cells above the substrate and a well formed in the substrate which contains the memory cells. The shielding conductor primarily shields the memory cells from external noise signals created by other conductors. The isolating well primarily shields the memory cells from noise signals created by substrate currents and alpha particles. Among other features the DRAM employs a logically complementary pair of charge storage capacitors and differential sensing to avoid the influence of noise on a single memory capacitor. The shielding conductor is formed by a mesh of conductors or an integral conductor which overlays the matrix of cells and connects to the well. External power supplies and references are also connected to the well and the shielding conductors.

Abstract: A circuit that provides a termination resistance to a transmission line includes a controllable termination resistor coupled between the transmission line and a termination voltage node. The circuit also includes a control circuit coupled to the controllable termination resistor and to a reference resistor. The control circuit matches the resistance of the controllable termination resistor to the resistance of the reference resistor.

Abstract: An electrically programmable read only memory device which has efficiency of electron injection from channel to floating gate is provided. This memory cell includes a control gate and floating gate between source and drain regions. The region under the floating gate has extremely small enhanced mode channel and N region. Therefore, this channel is completely depleted by the program drain voltage. The enhanced mode channel region is precisely defined by the side wall spacer technique. Also, the N drain region is accurately defined by the difference of side wall polysilicon gate and the first spacer.

Abstract: A method designates nets of a circuit for detailed parasitic impedance extraction (e.g., calculation of parasitic resistance and/or capacitance components of circuit interconnects) by comparing an estimated net impedance parameter with other circuit characteristics, such as the output resistance of a driver cell or the gate capacitance provided by load elements connected to the net. One or more threshold percentage parameters may be used in the comparison. Also, based on the designation, the estimated net impedance parameter or the detailed parasitic impedance value may be used for calculating logic delay through a logic cell driving the net. A program stored on a computer readable medium also operates to evaluate the parasitic impedance of circuit interconnects relative to other circuit characteristics and, depending on this evaluation, calculates the logic delay of a logic cell driving the net using an estimated net impedance parameter or detailed parasitic impedance parameter.

Abstract: A fabrication method for an electrically programmable read only memory device, which consists of a control/word gate and a MONOS control gate on the side wall of the control gate. The unique material selection and blocking mask sequences allow simple and safe fabrication within the delicate scaled CMOS process environment, of a sidewall MONOS control gate with an ultra short channel under the control gate, which involves double side wall spacer formation i.e., a disposable side wall spacer and the final polysilicon spacer gate.

Abstract: A DRAM cell capacitor and access transistor are described. Capacitor formation, access transistor fabrication and cell isolation methods are integrated by using isolation trench sidewalls to form DRAM capacitors and access transistors. A doped silicon substrate adjacent to the vertical sidewalls of the isolation trench provides one DRAM cell capacitor plate. The DRAM capacitor also contains a dielectric material that partially covers the interior vertical sidewalls of the isolation trench. A conductive layer covering the dielectric material on the vertical sidewalls of the isolation trench forms the second capacitor plate and completes the DRAM capacitor. A vertically oriented access transistor is formed over top of the capacitor. To accomplish this, an isolation dielectric is deposited and patterned to provide a support structure for gate electrodes of the vertical access transistor above the trench sidewall capacitors.

Abstract: Techniques for fabricating metal-insulator-metal (MIM) capacitive structures by chemical vapor deposition (CVD) help avoid the formation of a porous metal oxide film at the interface between the lower electrode and the insulating layer. One method of fabricating an integrated circuit includes depositing a first titanium nitride electrode layer on a wafer by CVD and subsequently depositing an insulating layer on the first electrode. The insulating layer can comprise a material selected from the group consisting of titanium oxide (TiOx), titanium oxynitride (TiOxNy), titanium oxycarbonitride (TiOxNyCz) and silicon oxide (SiOx), and is deposited by CVD without exposing the first titanium nitride electrode to atmosphere. A second titanium nitride electrode layer also is deposited on the insulating layer by CVD. The various layers of the capacitive structure, including the insulating layer, can be deposited in situ in a single CVD chamber.

Abstract: A method and system for decoding compressed MPEG2 bitstream video data utilizing a two row macroblock cache memory and algorithm for determining data overlap between a stored reference macroblock and a stored current macroblock to improve memory bandwidth requirements while producing specific decoding results required for MPEG2 video information.

Abstract: An integrated circuit comprised of a customized circuit portion and a programmable logic portion that is interfaced to the customized circuit. The custom circuit and the programmable circuit are fabricated on a common semiconductor substrate to achieve maximum cost savings and performance advantages over implementations in which an external PLD or other programmable device is interfaced to a custom circuit. Suitably, the customized circuit is designed with an ASIC design flow to optimize the performance, power consumption, and size of the customized circuit. In the presently preferred embodiment, the programmable circuit comprises a plurality of programmable logic cells suitably generated by, in one embodiment, a PLD compiler. Ideally, the relative size and placement of said PLD with respect to said customized circuit are selectable during a design phase of said integrated circuit. This provides flexibility in determining how much of an interim device need be devoted to programmable circuitry.

Abstract: A method for detection of hot-swap of disk drives in a storage subsystem devoid of special circuits for such detection and for buffering of bus signals. Typical prior designs utilize special circuits such as disk drive canisters for physically and electronically connecting the disk drives to the storage subsystem. These canisters provided electronic buffering to reduce or eliminate transient (noise and glitch) signals associated with hot-swap drive removal and insertion. In addition, such canisters provided special purpose circuits to inform storage subsystem control modules that a possible insertion or removal occurred by forcing a reset of the interconnection bus in response to detection of such transient signals. The present invention provides for such detection without need for such complex (e.g., costly) special purpose circuits.