Abstract: An improved satellite receiver front end architecture having a tuner chip and a demodulator/decoder chip. The tuner chip includes a lowpass filter having a configurable cutoff frequency, and the tuner chip uses a frequency signal to provide accurate adjustment of the cutoff frequency. A clock signal having a clock frequency is converted into a control voltage which determines the cutoff frequency of the lowpass filter. Consequently, the cutoff frequency may be increased by increasing the clock frequency, or decreased by decreasing the clock frequency. This configuration provides for improved cutoff frequency control in the presence of signal interference.

Abstract: A method and apparatus for transferring data from a host to a node through a fabric connecting the host to the node. A chip architecture is provided in which a protocol engine provides for on chip processing in transferring data such that frequent interrupts from various components within the chip may be processed without intervention from the host processor. Additionally, context managers are provided to transmit and receive data. The protocol engine creates a list of transmit activities, which is traversed by the context managers, which in turn execute the listed activity in a fashion independent from the protocol engine. In receiving data, the context managers provide a mechanism to process frames of data originating from various sources without requiring intervention from the protocol engine. When receiving data, the context managers are able to process frames from different sources, which arrive out of order.

Abstract: A protocol translation cable assembly includes a first connector having a first plurality of pins, a second connector having a second plurality of pins, and an electrical cable coupling the first connector to the second connector, where the electrical cable includes a plurality of conductors. The protocol translation cable assembly further includes translation circuitry coupled to at least some of the plurality of wires of the electric cable at points between the first plurality of pins of the first connector and the second plurality of pins of the second connector. The translation circuitry preferably derives its power from the electrical cable such that separate power supplies are not required. The cable assembly therefore provides transparent "plug-and-play" capabilities.

Abstract: An integrated circuit buffer includes a core output terminal, a pad terminal, a pad pull-down transistor, a pad pull-up transistor, a pull-down control circuit and a pull-up control circuit. The pad pull-down transistor and the pad pull-up transistor are coupled to the pad terminal and have pull-up and pull-down control terminals, respectively. The pull-down control circuit is coupled between the core output terminal and the pull-down control terminal. The pull-up control circuit is coupled between the core output terminal and the pull-up control terminal. A pull-up voltage protection transistor is coupled in series between the pad pull-up transistor and the pad terminal and has a control terminal which is coupled to the pad terminal through a voltage feedback circuit.

Abstract: The present invention provides a semiconductor protection device in a substrate having a first type of conductivity. The semiconductor protection device includes two vertical bipolar transistors. A well region is located within the substrate having a second type of conductivity with a base region within the well region having a first type of conductivity. A first doped region having the second type of conductivity and a second doped region having a first type of conductivity are located within the well region. A third doped region having the second type of conductivity and a fourth doped region having the first type of conductivity are located within the base region. A doped region having a first type of conductivity is located within the substrate. This doped region is connected to the fourth doped region.

Abstract: Methods and apparatus are described for managing high-bandwidth incoming digital data streams, such as MPEG encoded data streams, while reducing memory requirements. Frames of incoming data are divided into smaller slices, for example four slices per frame. A sequencing memory is used to store frame store memory addresses pointing to locations in the frame store buffer where slices of data are stored. As incoming data is stored in the frame buffer, corresponding start location addresses are stored in the sequencing memory, and corresponding bits in a status register are marked as busy. Conversely, as data is read out of the frame store for decoding or reconstruction, the corresponding bit in the status register is changed to the free status, as each slice of data is processed. This procedure and corresponding architecture reduces frame store memory requirements.

Abstract: An apparatus and method of making a void free interface between a heatspreader and pressure sensitive adhesive (PSA) by attaching them in an air free environment. The PSA is placed on a pedestal in a vacuum chamber assembly, then the heatspreader is placed on top of the PSA and the chamber is closed. The air is removed by a vacuum means, creating an air free environment. Once the desired vacuum is obtained and the air is removed, pressure is applied to the heatspreader and PSA, joining them together with a void free interface between them. After joining, the vacuum is released and the vacuum chamber assembly is opened so that the heatspreader with PSA attached can be removed. The heatspreader with PSA is now ready for use with a semiconductor package. Additionally, the heatspreader with PSA may be joined to the integrated circuit die of a semiconductor package in an air free environment by the same process (using vacuum and pressure) as describe above.

Abstract: A method and apparatus for testing an integrated circuit die including a probe card (10) having a plurality of surface mount pads (45) arranged in a pattern (50) substantially corresponding to an area array pattern of die bumps (25) on the IC die. The pads and the die bumps are respectively electrically connected to each other with conductive probes (30). A plurality of test contacts (55) located around the periphery of the probe card (10) are in electrical contact to each surface mount pad (45) with electrical traces (65). An integrated circuit tester (60) having a plurality of test channels is electrically connected to a selected test contact (55) of the probe card (10), thereby forming a continuous conductive path between the integrated circuit tester (60) and the die bumps (25) on the IC die.

Abstract: A method and device for automatically verifying results of a simulation is disclosed. External stimuli are applied to a device under test and observed output is generated in response thereto. The observed output is applied to a non-cycle accurate model of the device comprising procedures which simulate significant events corresponding to the significant events of the observed output. Verification conditions are set according to the aspects of the device under test which are being tested and the verification conditions are applied to the output from the non-cycle accurate model. The verification conditions are associated with a procedure of the model such that the verification condition is verified before or after execution of the procedure. In addition, the verification conditions may be executed at the end of the simulation to ensure that all events which should have occur, have occurred.

Abstract: A process of forming on an integrated circuit substrate at least two different gate masks having different lengths is described. The process includes: (i) providing the integrated circuit substrate having a surface; (ii) depositing on the surface a gate layer; and (iii) masking portions of the gate layer using a reticle having at least two die patterns including a first die pattern defining an image of a first gate electrode having a first length and a second die pattern defining an image of a second gate electrode having a second length, the first length being different from the second length and relative positioning of the image of the first gate electrode in the first die pattern and of the image of second gate electrode in the second die pattern is substantially similar.

Abstract: Apparatus, and an associated method, for generating multi-bit sequences used, for instance, to form an address pointer or a data pointer of a computer system. The circuitry is embodied in a single-cycle path and is operable to generate an output sequence which is of a bit length which is a multiple of an input sequence. In one implementation, the circuitry is used to generate 48-bit address pointers and 16-bit data pointers.

Abstract: An E-beam generator and detector arrangement sends an electron beam through a series of differentially evacuated vacuum chambers of small size to detect faulty circuitry in individual semiconductor devices. The vacuum chambers are open to one end and are sealed by the semiconductor device without contacting the vacuum chambers. A laser generator is operated by a control system with the E-beam generator and detector arrangement to provide a laser beam in a known physical relationship to the electron beam to correct detected faulty circuitry in the semiconductor devices. The E-beam generator and detector arrangement confirms the correction without further handling of the semiconductor device.

Abstract: Apparatus for demodulating digital video broadcast signals with an improved mechanism for automatic frequency control including data modulated on a multiplicity of spaced carrier frequencies. The apparatus includes an analog to digital converter for providing a series of digital samples of the broadcast signal, a Fourier Transformer for analyzing the samples to provide a series of data signal values for each carrier frequency, signal processor for processing the series of data signal values including the phase-error-correcter, and automatic frequency controller for controlling the frequency of the signals input to the Fourier Transformer. The automatic frequency controller includes coarse frequency controller for controlling the frequency in terms of increments of the carrier spacing frequency, and fine frequency controller for controlling the frequency for values less than a single carrier spacing frequency interval.

Abstract: A circuit assembly comprising a substrate, a first set of contacts, a second set of contacts, and a third set of contacts. Also, a plurality of electrically conductive lines located on the substrate providing electrical connection between the first set of contacts, the second set of contacts, and the third set of contacts, wherein the plurality of electrically conductive lines are configured such that data can be transferred between the first set of contacts, the second set of contacts and the third set of contacts. A first die is electrically connected to the first set of contacts, and a molding compound surrounds the substrate, wherein the molding compound is formed such that the second set of contacts is exposed allowing electrical connection of the second die to the second set of contacts.

Abstract: Gaseous reactants capable of depositing a thin film on a semiconductor substrate are introduced into a deposition zone of a deposition apparatus through a gaseous reactants dispersion apparatus having rounded corners and smoothed anodized surfaces and maintained at a temperature ranging from about 70.degree. C. to about 85.degree. C., and preferably from about 75.degree. C. to about 80.degree. C., to inhibit the deposition and accumulation on such surfaces of charged materials capable of generating particles which may cause damage to the semiconductor substrate.

Abstract: Apparatus and method for assembling solder balls in a selected one of several different patterns for delivery to connector pads on an integrated circuit package, or other receiver, includes a universal template containing holes at locations in an aggregate pattern of all hole locations for the several different patterns, and includes a subtemplate for each individual different pattern that contains posts at locations for insertion from the rear of the template into holes therein at locations where no surface recess is desired. The universal template may remain aligned with an assembly jig or holder of packages while only the subtemplate is changed to change the surface pattern of holes into which solder balls may then be distributed.

Abstract: A method for improving the fault coverage of functional tests for integrated circuits by establishing a design-specific low voltage functional screening procedure. In the disclosed embodiment of the invention, a reduced voltage test threshold is established by comparing the results of an iterative test procedure executed on a set of known good integrated circuits and integrated circuits which have passed traditional functional test programs but manifested problems in the field. For a given device under test, the iterative procedure commences by applying a system clock and nominal power supply voltage. A set of functional test vectors is then executed on the device using automated test equipment (ATE). The results are compared with expected test results to determine if the device is a passing device under the initial test conditions. If so, the power supply voltage is decremented by a predetermined value and the test process is repeated.

Abstract: Apparatus and an associated method calculates a CRC remainder for a block of data, such as a block of data retrieved from a CD-ROM device. CRC calculations are performed to provide assurances of data integrity subsequent to error corrections of the block of data. CRC remainders associated with N powers of two are stored in the look-up table. When calculating the CRC remainder, selected values stored in the look-up table are retrieved and combined to form the CRC remainder for the block of data.

Abstract: A semiconductor package is disclosed. According to one embodiment, the package comprises a substrate having a top surface with traces thereon and a bottom surface with solder balls thereon, the substrate comprising at least three material layers defining at least four substantially planar metal layers, wherein one of the metal layers comprises a reference layer that serves as a reference to both traces on a metal layer above the reference layer and traces on a metal layer below the reference layer. A semiconductor die is mounted to the substrate and bonding wires electrically connect the semiconductor die to the traces on the top surface of the substrate. The traces on the top surface of the substrate are electrically connect to the solder balls through vias and possibly through routing on another metal layer.

Abstract: An audio decoder is provided with a programmable and re-configurable downmixing process. In one embodiment, the audio decoder includes a control module and a data path. The data path is configured to read, scale, add, and write audio samples to and from various audio channel frame buffers. The control module implements state diagrams which specify various control signals for directing the operations of the data path. The control module implements state diagrams for directing windowing and downmixing operations. The order in which these operations are performed may be reconfigurable, i.e. downmixing may be performed before or after windowing. This reconfigurability advantageously permits the system designer to trade a slight audio quality enhancement for a decreased memory requirement for some speaker configurations. The downmixing operation requires scaling coefficients which are provided by the control module.