Abstract: The present invention provides apparatus and a process for efficiently removing particles generated during a laser marking of the semiconductor wafer substrate, thereby improving the yield. The process of the invention for marking a semiconductor wafer substrate by a beam of laser radiation comprises the steps of flowing a gas over a marking region at a predetermined flow rate and removing the gas from the marking region at the same predetermined flow rate, thereby generating a gas flow having a predetermined flow rate over and adjacent the marking region so that particles produced from the semiconductor wafer substrate while it is being marked will be removed. In a preferred embodiment, the semiconductor wafer substrate may be mounted with its upper surface to be marked directed downwardly while the laser marking beam is directed upwardly to the substrate.

Abstract: An isolation trench in a silicon semiconductor substrate is provided with a barrier region containing nitrogen atoms formed in the trench, contiguous with the silicon semiconductor substrate surfaces of the trench. The novel isolation trench structure of the invention is formed by forming an isolation trench in a silicon semiconductor substrate; forming in the isolation trench a barrier region by treating the trench structure with nitrogen atoms from a nitrogen plasma; and then forming a silicon oxide layer over the barrier region in the trench to confine the nitrogen atoms in the barrier region. In a preferred embodiment, a silicon oxide liner is first formed over the silicon semiconductor substrate surfaces of the trench, and then the trench structure is treated with nitrogen atoms from a nitrogen plasma to form, on the silicon semiconductor substrate surfaces of the trench, a barrier layer which contains silicon atoms, oxygen atoms, and nitrogen atoms.

Abstract: A transmission system for transmitting a signal from a host to a transmission medium is disclosed. The transmission system includes a current-mode digital-analog converter, an on-chip low-pass filter, a line driver, and output impedance control. Further, a method for transmitting a signal from a host to a transmission medium using on-chip filtering is disclosed. The transmission system and method can be used in transmission of Ethernet signals onto an unshielded twisted pair cable. In addition, with appropriate modification, the transmission system and method can be used for transmitting ATM or other signals onto a transmission medium.

Abstract: A device to turn on a disk formatter's write gate and NRZ line drivers with minimal delay from a sector pulse. The device utilizes a look-ahead scheme to asynchronously qualify a sector pulse to drive the write gate and enable the NRZ output drivers. The write gate and NRZ line drivers are conditionally enabled by a sector pulse and are held in the enabled state until the disk formatter provides an enable signal. The enabled NRZ line drivers provide binary zeros until actual data is provided to the drivers.

Abstract: Disclosed is a failure analysis tool including a production tester electrically coupled to a test IC in such a manner that it can test the IC in a conventional manner (e.g. by providing a series of dynamic vectors), and also provide an OBIC signal to an OBIC detection system. This is accomplished by providing power to the IC through a voltage source having a non-zero internal resistance while the OBIC signal is generated, thus preventing the OBIC signal from shorting to ground when it is received at the power supply. Failure analysis is conducted by first performing functional testing with a production tester until a failing state is identified. While this functional testing is being performed, the internal resistance of the voltage source is set to zero. Then, when the failing state is identified, the internal resistance of the voltage source is set to a non-zero value and the IC is scanned by an optical beam to generate OBIC signals indicating the locus of the failure.

Abstract: A luminaire reflector formed from a sheet of reflective material is folded and curved by hand to form a self-standing reflector having a predetermined three-dimensional reflector shape. The sheet of reflective material includes integral panels that are joined to adjacent panels through fold lines that allow the panels to be folded by hand. The panels have free edges that are folded and/or curved into abutting relationship. The panels include locking members and positioning tabs formed adjacent the free edges to retain the reflector in a predetermined three-dimensional reflector shape. Methods of making a self-standing reflector for a luminaire are also disclosed.

Abstract: An object of the present invention is to provide for a method and apparatus to partition high fanout nets into smaller subnets. Said method includes the steps of identifying elementary pairs of pins in the net, each such elementary pair defining a line; eliminating lines such that a planar graph is formed; eliminating further lines such that a spanning tree is formed, said spanning tree connecting each pin in the net; identifying basic elements, each basic element forming a portion of said spanning tree; and constructing a connected cover for said net, said connected cover comprising a plurality of said basic elements.

Abstract: A DMA controller including an XOR FIFO buffer and XOR circuitry for computation of parity. The DMA controller resides within a RAID controller and establishes a direct data connection from host memory to subsystem local memory in order allow the CPU to perform other functions. The DMA controller accesses data segments from host memory corresponding to blocks of data within a disk stripe. As the data is transferred from host memory to subsystem local memory, the XOR circuitry simultaneously computes the parity corresponding to the successive data segments. Computing parity substantially simultaneously with the DMA data transfer reduces memory bandwidth utilization on the memory bus of the RAID controller. The parity is stored in the XOR buffer. Once parity is computed for a portion of data segments corresponding to a data stripe, the parity is transferred to local memory for retention.

Abstract: A routing scheme for a multilayer printed wiring board or semiconductor package is disclosed. Each of a first group of electrical contacts such as bond pads is disposed on a first surface and is electrically coupled to one of a plurality of conductive surface connectors such as vias. Each of a second group of electrical contacts is disposed on the first surface and is routed by one of a second plurality of traces. Each of a plurality of short traces couple each of the bond pads in the first group with corresponding ones of the vias, which in turn are electrically coupled to one of a plurality of first traces on the second surface. The orientation between certain electrical contacts in the first group and their associated vias is different than the orientation between certain other electrical contacts in the first group and their associated vias. This varying orientation allows greater routing density on the second surface.

Abstract: Radio frequency photo conductive decay is used to monitor a small piece of high-grade silicon to determine if copper contamination has been removed from a probe tool. A probe tool is placed in contact with a small "waferette" of silicon repeatedly until the copper signal is diminished, indicating that the tool may be used for other products without concern for copper contamination.

Abstract: In a storage target device controller capable of managing multiple command contexts, methods and associated apparatus are provided for enabling simultaneous, independent operation of the disk channel and the host channel. In a multi-context target device controller, an active context initiates a requested exchange of data blocks between the host channel and the disk channel of the target device. The controller may swap the active context with an inactive context to better utilize resources of the target device such as the host channel bandwidth. The present invention provides for continued independent operation of the host channel and the disk channel. Counters associated with the active context are only updated by operation of the disk channel if the active context is the initiating context of the disk operations.

Abstract: Method and apparatus for accelerating write operations logging write requests in a log structured cache and by expanding the log structured cache using a cache-extension disk region. The log structured cache include a cache memory region partitioned into one or more write cache segments and one or more redundancy-data (parity) cache segments. The cache-extension disk region is a portion of a disk array separate from a main disk region. The cache-extension disk region is also partitioned into segments and is used to extend the size of the log structured cache. The main disk region is instead managed in accordance with storage management techniques (e.g., RAID storage management). The write cache segment is partitioned into multiple write cache segments so that when one is full another can be used to handle new write requests. When one of these multiple write cache segments is filled, it is moved to the cache-extension disk region thereby freeing the write cache segment for reuse.

Abstract: A composite metal line structure for an integrated circuit structure on a semiconductor substrate is disclosed which comprises: a low resistance metal core layer; a first thin protective layer of electrically conductive material on the upper surface of the metal core layer capable of protecting the metal core layer from reaction with tungsten; a layer of tungsten formed over the first protective layer to function as an etch stop layer for vias subsequently formed in an overlying dielectric layer; and a second thin protective layer of electrically conductive material over the tungsten layer and capable of functioning as an antireflective coating (ARC).

Abstract: A process for forming low k silicon oxide dielectric material having a dielectric constant no greater than 3.0, while suppressing pressure spikes during the formation of the low k silicon oxide dielectric material comprises reacting an organo-silane and hydrogen peroxide in a reactor chamber containing a silicon substrate while maintaining an electrical bias on the substrate. In a preferred embodiment the reactants are flowed into the reactor at a reactant flow ratio of organo-silane reactant to hydrogen peroxide reactant of not more than 10.6 sccm of organo-silane reactant per 0.1 grams/minute of hydrogen peroxide reactant; and the substrate is biased with either a positive DC bias potential, with respect to the grounded reactor chamber walls, of about +50 to +300 volts, or a low frequency AC bias potential ranging from a minimum of +50/-50 volts up to a maximum of about +300/-300 volts.

Abstract: The nonvolatile semiconductor memory device of the invention includes: a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first and second surface regions; a channel region formed in the first surface region of the semiconductor substrate; a source region and a drain region which are formed in the surface of the semiconductor substrate so as to interpose the channel region therebetween; a first insulating film formed on the surface of the semiconductor substrate; a floating gate formed on the first insulating film; and a control gate capacitively coupled to the floating gate via a second insulating film. The first surface region is an upper surface of an epitaxially grown layer formed on the second surface region.

Abstract: A multiple well formation is provided in a CMOS region of a semiconductor substrate to provide enhanced latchup protection for one or more CMOS transistors formed in the wells. The structure comprises an N well extending from the substrate surface down into the substrate, a buried P well formed in the substrate beneath the N well, a second P well extending from the substrate surface down into the substrate, and an isolation region formed in the substrate between the N well and the second P well. The buried P well may extend beneath both the N well and the second P well in the substrate. In a preferred embodiment of the invention, the N well and the second P well are each implanted in the substrate at an energy level sufficient to provide a dopant concentration peak in the substrate below the depth of the isolation region to provide punch through protection and to provide a channel stop beneath the isolation region by proving a P-N junction between the N well and P well beneath the isolation region.

Abstract: In order to reduce memory bandwidth when predicting B-frames from stored anchor frames in an MPEG-2 video decoder, memory access requests (20) to external memory (14) storing anchor frames are selectively suppressed (18) so that only data is accessed which is required for the current data to be displayed. To still further reduce memory bandwidth, a prediction type (frame picture-frame prediction-half pel filtering) which requires a large number of memory requests is approximated to a type (field prediction) which requires half as many memory requests.

Abstract: An electrostatic protected integrated circuit (IC) substrate and a method of making an integrated circuit package with the electrostatic protected IC substrate includes an IC substrate, having a plurality of electrical traces formed on the top of the IC substrate with the electrical traces extending from an IC chip mounting area near the center to the periphery of the IC substrate. Electrically shorting the electrical traces together with a conductive material such as conductive tape or epoxy, thereby, protecting the IC substrate against the accumulation of static charges during the assembly of the IC chip on the IC substrate. The IC chip is mounted in the mounting area on the IC substrate and the conductive material is removed before final testing.

Abstract: A single chip communications controller responsive to control program commands, implements at least three major communication function standards simultaneously by using a superscalar processor coupled to a multi-functional communication interface unit, and a supportive memory system via a common communication bus.

Abstract: A method determines the behavior of a logic cell that receives input signals resulting in a narrow pulse or "glitch." If the pulse width of the output pulse is narrower than a pulse rejection period, the output pulse is rejected and is not propagated to subsequent logic cells connected to the output. The method employs a first internal logic cell model which is assigned an inertial delay function, and a second internal logic cell model which is assigned a transport delay function. In combination, the first and second logic cell models result in an effective propagation delay value, subject to the pulse rejection feature. An exemplary VHDL model is disclosed. A program product embodies a logic cell model in VHDL providing pulse rejection capabilities for output pulses with pulse width smaller than a pulse rejection period.