Abstract: The present invention includes a method and system for improving performance of a receiver at a low signal-to-noise ratio. According to a first aspect, an encoded signal is received. The encoded signal is decoded to recover information in the encoded signal. Next, a threshold is ascertained in response to the recovered information, the threshold indicating a maximum number of acceptable errors in the recovered information. It is determined if the errors in the recovered information are in excess of the ascertained threshold. Information is then extracted from the encoded signal without decoding. The extracted information is output when the errors in the recovered information are in excess of the ascertained threshold. In all other instances, the recovered information is output. According to a second aspect, recovered signal data is output, the recovered signal data being either the recovered information or the extracted information.

Abstract: A method and apparatus for determining when an approaching object has contacted a sensor panel. The method includes the steps of (a) using a controller which is connected to the sensor panel, (b) determining a value for the approaching object based on a current flow between the sensor panel and the controller, (c) repeating step (b) until the value has reached a maximum value, and (d) generating a signal when the value has reached the maximum value to indicate that the object is contacting the sensor panel.

Abstract: A method of fabricating a semiconductor wafer is disclosed.

Abstract: A method, system, and data structure for encoding a block of data with redundancy information and for correction of erasure type errors in the block using the redundancy data. In particular, the invention is particularly applicable to disk array storage subsystems which are capable of recovering from total or partial failures of one or two disks in the disk array. Still more specifically, the invention is applicable to RAID level 6 storage devices. A given data block of data is translated into a code block of n.sup.2 elements including 2n XOR parity elements for redundancy. Each code block is manipulated as a square matrix, of n.sup.2 elements with parity elements along the major diagonals of the matrix and data elements in the remainder of the matrix. Each parity element is a dependent variable whose value is the XOR sum of the (n-2) data elements in a minor diagonal which intersects it.

Abstract: The present invention performs decoding of trellis coded modulated data using a conventional decoder by splitting up the tasks of estimating the uncoded portion and estimating the coded portion into separate tasks. The task of estimating the coded portion is performed based on a transformation on the input symbols and by taking advantage of the symmetry of the constellation associated with the modulated data when referencing a lookup table. The lookup table may also be designed to be smaller than a straight forward implementation by taking advantage of the same symmetry of the constellation.The alteration of the data is then corrected for, resulting in a smaller constellation (Bi Phase Shift Key for 1 coded bit per symbol systems, Quadrature Phase Shift Key for 2 coded bits per symbol systems) mapping only the coded portion of the data. This allows a conventional Viterbi decoder to estimate the coded portion.

Abstract: A semiconductor device package is presented for housing an integrated circuit which includes bonding fingers located within a conductive ring structure and routed to device terminals on an underside surface of the semiconductor device package. The semiconductor device package includes a die area defined upon a planar upper surface, a conductive ring surrounding the die area, and a first set of bonding fingers arranged within the conductive ring. The die area is dimensioned to receive the integrated circuit. The conductive ring may be a power ring or a ground ring. The conductive ring and the first set of bonding fingers are located within a first signal layer adjacent to the upper surface. A set of bonding pads which serve as device terminals reside within a second signal layer adjacent to a planar underside surface.

Abstract: A demodulator suitable for implementation in a single chip for demodulating digital video broadcast signals including data modulated on a multiplicity of spaced carrier frequencies, wherein an input broadcast signal is converted to a frequency sufficiently low to enable analog digital conversion of the signal. The demodulator includes an analog to digital converter for converting the broadcast signal to a series of digital samples; a real to complex converter for converting each digital sample to a complex number value; Fourier transformer for analyzing the complex number values to provide a series of data symbol values for each carrier frequency; a signal processor for receiving the data symbol values and providing an output for decoding; and a timing synchronizer for synchronizing the Fourier transformer with the symbol periods of the broadcast signal.

Abstract: A hard disk simulator that comprises a timing generator controller coupled to receive address, data and control signals; a timing generator for providing a pulse in response to signals received from the timing generator controller; and an address generator coupled to receive the control or index pulse and a programmable frequency clock to generate addresses for a hard disk simulator. The address generator includes an offset counter that generates values in response to the programmable frequency clock and the control pulse. The address generator also receives a base address that corresponds to a hard disk track. The offset counter values and the base address are combined to provide an address. The present invention also includes a method of simulating a hard disk including the step of adding an offset value to a base value to simulate rotational latency of the hard disk.

Abstract: A method of creating a layer-to-layer alignment mark in a semiconductor wafer includes the step of depositing a first conductor layer on a substrate associated with the semiconductor wafer. The method also includes the step of fabricating a number of alignment trenches in the first conductor layer. Moreover, the method includes the step of depositing a first insulator layer on the first conductor layer so as to fill the number of alignment trenches. Yet further, the method includes the step of removing material associated with the first insulator layer from the number of alignment trenches such that an upper surface of the first conductor layer and an upper surface of the first insulator layer define a first alignment step feature which possesses a predetermined height. The method also includes the step of depositing a second conductor layer on the semiconductor wafer subsequent to the removing step. A semiconductor wafer is also disclosed.

Abstract: A memory circuit which uses multiple storage mechanisms in each of its memory cells. In one embodiment, the memory circuit includes an array of cells in which each cell has multiple storage elements. At least one of the storage elements performs its function in a different way than the rest of the storage elements. This use of multiple storage mechanisms allows for a greater freedom in memory cell design and allows for the simultaneous storage of multiple states in a single memory cell. Broadly speaking, the present invention contemplates a memory core comprising an address decoder, an array of cells, and a sense amplifier. The address decoder is configured to receive an address and responsively assert a selected word line. The array of cells includes a selected cell coupled to the selected word line, and each cell in the array of cells includes at least two storage elements.

Abstract: A system and method for representing a system level RTL hardware design using an HDL independent RTL representation and translation into synthesizable RTL code. The present invention creates an object-oriented library which can be used to implement RTL hardware designs in terms of HDL independent objects. Instead of implementing multiple HDL instances of hardware modules, the invention enables software tool programmers to implement one HDL-independent instance of the hardware module. As a result, a programmer can focus his efforts on generating the functionality of the module and can be relieved from the time consuming task of generating the detailed syntax of multiple HDLs. The present invention also maintains synchronization across multiple HDLs so that a software designer can generate HDL code for any supported HDL, e.g., Verilog or VHDL, thus making software maintenance easier.

Abstract: A memory controller features programmable delay buffers that allow the memory interface signals to be automatically adjusted. By fine tuning the delay values, the memory controller can compensate for impedance characteristics that affect the memory interface timing. The memory controller includes a built-in self test mode, in which it runs a series of memory tests using a plurality of different delay combinations for the delay buffers. After running the built-in self test, the memory controller programs the delay buffers to values which allow the memory transactions to occur without errors, ensuring optimal memory interface timing.

Abstract: A technique for mass distributing software products, especially integrated circuit design tools and design libraries, while allowing only a selected portion of the products to be loaded onto and used on a computer. One or more volumes of CD-ROM contains one or more software products, each of which are encrypted with a key code. The CD-ROMs are mass distributed to customers. A separate configuration file, uniquely configured for each customer, contains a list of only the selected portion of software products, and contains the key codes for decrypting only those products. A loader module is provided for controlling the decryption and loading of only the selected portion of products, based on information in the configuration file. Each software product is hierarchically arranged by class, file set and file, and files may be shared between products.

Abstract: An fast program, ultra-high density, dual-bit, multi-level flash memory process, which can be applied to a ballistic step split gate side wall transistor, or to a ballistic planar split gate side wall transistor, which enables program operation by low voltage requirement on the floating gate during program is described. Two side wall floating gates are paired with a single word line select gate, and word lines are arranged to be perpendicular both the bit lines and control gate lines. Two adjacent memory cells on the same word line do not require an isolation region. Also, the isolation region between adjacent memory cells sharing the same bitline is defined by the minimum lithography feature, utilizing a self align fill technique. Adjacent memory cells on the same word line share bitline diffusion as well as a third poly control gate. Control gates allow program and read access to the individual floating gate.

Abstract: Methods and apparatus pertaining to flip chip ball grid array packages are disclosed. A substrate comprises a base layer with a dielectric laminated thereon such that a cavity in the dielectric exposes the base layer. A die is then mounted to the exposed portion of the base layer. Preferably, an upper portion of the dielectric forms a frame for receiving a heat spreader.

Abstract: The present invention is directed to the encoding and decoding of a digital signal. The encoding process results in a rate-1/n convolutional code derived from a rate-1/2 convolutional code. The process includes: selecting a base convolutional encoding rate of rate-1/l, where l is an integer; selecting an output encoding rate of 1/n, where n is an integer greater than 1; encoding an input digital signal into a convolutional code comprised of signals S(0) through S(l-1), the convolutional code having the rate 1/l convolutional code encoding rate; and providing a rate-1/n convolutional code, which is derived from the rate-1/l convolutional code, the rate-1/n convolutional code having N(i) copies of the rate-1/l signals S(i), where i is from 0 through 1-l and where the sum of N(i) is equal to n.

Abstract: A process for designing an integrated circuit chip includes specifying a set of cells, a set of wiring nets for interconnecting the cells, and a set of regions on the chip in which the cells are to be placed. An assignment of the cells of the set to the regions is generated, and the set of cells is randomly divided into a first subset of cells which remain in the assignment, and a second subset of cells which are removed from the assignment. Penalties are computed for assigning the cells of the second subset to the regions respectively, and the cells of the second subset are assigned to the regions such that a total penalty thereof is minimized. The process is repeated iteratively with the size of the second subset being progressively reduced relative to the size of the first subset until an end criterion is reached.

Abstract: A video processing system that processes vertical column of pixels from individual fields is disclosed. The video processing system processes pixels from an even field independent of the pixels in the odd field, and vice versa. The video processing system preferably includes a system memory for storing fields of input video images and a vertical filter coupled to the system memory via a data bus. The field data is retrieved from the system memory by the vertical filter and processed as individual fields. The vertical filter preferably calculates a 2.times. enlargement of the input image, although the filter can be adapted to enlarge by different factors if desired. The enlargement process generally involves representing an input image with twice as many lines of pixels values as the initial image. The values that are used to represent the enlarged pixels are preferably weighted averages of the pixels from an input pixel field.

Abstract: The present invention is a method to minimize the firmware overhead for multi-track transfers. To this end, the present invention provides a transfer control table. The table is used to manage sector defects or other transfer adjustments. Each entry of the table contains an affected PSA and a corresponding control instruction. The control instruction includes an action such as an interrupt/branch, take no action, skip the sector or skip the following indicated sectors. The interrupt/branch bit causes an preferably when the last sector of a track has been read or written. The table is either entirely generated at the same time or is generated to provide for a track transfer. In the latter case, the remaining table entries are generated during the platter revolution or the track seek. The method provides for minimum microprocessor intervention. To that end, the microprocessor is interrupted only at the end of the multi-track transfer.

Abstract: A high voltage transistor, formed in a bulk semiconductor material, has a gate region defined by a relatively thick field oxide and a source and drain on opposite sides of the field oxide.