Abstract: Circuitry for testing and comparing ESD protection structures is provided on a semiconductor integrated circuit. Analysis of charge transmitted to a test capacitor on board the chip provides for improved accuracy in evaluating performance of the ESD protection structure. Moreover, multiple ESD structures can be implemented and accurately compared to one another on a test chip as described. The disclosed methods and apparatus are usefull in reduced turn-around time and more accurate evaluation and comparison of ESD protection structures in integrated circuits.

Abstract: An arrangement and method for making a gate array architecture locates the well taps at the outer corners of each gate cell. The power buses are also located at the outside of the gate cell as well, enabling sharing of the well taps and the power buses. The location of the well taps at the outside corners of the standard cell reduces the number of transistors in a single repeatable cell from eight transistors to four transistors.

Abstract: An electronic semiconductor device package, the package comprising: a substrate having traces; a die attached to the substrate; first level interconnects of the die to the traces of the substrate; and a stiffener attached to the substrate, wherein the stiffener comprises at least one slot. A system for attaching a heat sink to an electronic semiconductor device package, the system comprising: a stiffener of the electronic package which is attachable to the electronic package; a clip which secures the heat sink to the stiffener; and at least one slot in the stiffener which receives the clip. A method of detachably attaching a heat sink to an electronic semiconductor device package, the method comprising: attaching a stiffener to the package, wherein the stiffener comprises at least one slot; positioning a heat sink adjacent the stiffener; and engaging a clip with the slot and the heat sink, wherein the heat sink is secured to the stiffener by the clip.

Abstract: A DRAM memory array is organized hierarchically into groups of DRAM segments, bit blocks within segments, and memory cells within bit blocks, arranged in rows and columns. A control and logic circuit extends along the rows and columns and segment buses extend from the control and logic circuit to the DRAM segments. Partial decoding of the address and control signals occurs in the control and logic circuit and the partially decoded control and address signals are supplied on the segment buses. Adaptable memory operations are controlled in the control and logic circuit, such as redundant element substitution, data block addressing, multiplexing of the data bit width signals available at the DRAM segments to the width required by a system bus. This flexibility allows various physical organizations of the DRAM array.

Abstract: Method and apparatus for transferring data on a voltage biased data line are disclosed. In one embodiment, there is provided a bus interface for controlling a differential bus having a differential data line that includes a first bus line and a second bus line. The bus interface includes a bus controller circuit, an impedance network, and a controllable biasing circuit. The bus controller circuit is coupled to the differential bus and is configured to (i) control transfer of data across the differential bus, and (ii) generate a biasing control signal prior to data transfer on the differential data line. The impedance network is coupled to the first bus line and the second bus line and is configured to substantially match a characteristic impedance of the differential data line.

Abstract: Methods and associated apparatus within a RAID subsystem having redundant controllers define a private LUN as a data storage area known and accessible to all controllers in the system and used by them for diagnostic purposes. The methods involve sending a diagnostic write command to a first controller with instructions for it to write test data to the private LUN. This first controller writes this test data to the private LUN. A second controller, in response to another diagnostic command, then reads this test data from the private LUN and compares it to expected values provided in the diagnostic command. Using the results, it can then be determined which controller, if any, failed. If the first controller fails, then the second controller takes over ownership of portions of the data storage area assigned to the first controller. The private LUN is preferably striped across all channels used by the controllers to communicate to commonly attached disk drives.

Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed.

Abstract: The present invention provides for novel off-axis illuminator lens masks for semiconductor photolithographic projection systems. The masks are rotationally symmetric along axes 60.degree. or 120.degree. apart. Such masks can increase the contrast 30.degree. and 60.degree. with respect to the X and Y axes of an integrated circuit in a semiconductor wafer for the optimum printing of conducting lines along these directions.

Abstract: A ball grid array package (BGA) according to the present invention has an interposer between a bond pad on the lower surface of the substrate and the solder ball. The interposer has a conductive portion in contact with the bond pad surrounded by a nonconductive or insulating portion. The conductive portion in contact with the bond pad is sufficiently constrained from widening during a subsequent reflow process by the presence of the nonconductive or insulating portion. The contact with the bond pad is sufficiently small to allow traces to pass near the bond pad substantially directly en route to another bond pad. The nonconductive portion also prevents subsequently-applied encapsulant from coming in contact with and contaminating the bond pad. The elevated surface of the interposer, i.e. the surface of the interposer furthest from the bond pad, supports the solder ball, and is sufficiently wide to support the solder ball without allowing the solder ball to come in contact with the traces.

Abstract: A PBGA package includes PBGA member, a stiffener ring, and a stiffener fixture which includes a retaining recess having a floor for receiving the stiffener ring and includes a ledge positioned above the recess floor for receiving the PBGA member. An adhesive layer is applied to the stiffener ring, which is adhered to the PBGA member. The stiffener ring and PBGA member are essentially coplanar to less than 8 mils. A top plate is placed on top of the PBGA member and the ring and member are secured together tightly.

Abstract: A method for comparing intermediate test files having different file formats used to test integrated circuitry is provided. The method initially receives intermediate test files from an ATPG tool or a manually run simulation. The ATPG tool or manually run simulation provides data in a .wgl format for testing, and is a non-simulatable format, and the ATPG tool also provides a second intermediate file comprising a file or files in a simulatable format. All files contain event data used for testing. The intermediate test files are converted to files having a common format. The invention then compares the converted files to determine mismatches between the converted files. This comparison comprises evaluating the common format files and generating a pass/fail flag based on the results of the evaluation. Mismatches between the common format are corrected if the flag indicates that the files are not identical.

Abstract: An apparatus and method for packaging an integrated circuit having a semiconductor die with electronic circuitry disposed thereon includes lead frames for mounting thereon solder balls of a ball grid array packaging structure. In one embodiment, the semiconductor die is coupled to conductors of the lead frame via gold wires attached to both the semiconductor die and the lead frame. The lead frame is encapsulated in plastic with apertures disposed therein for exposing upper and lower portions of conductors of the lead frame. The apertures are filled with solder balls to contact both the upper and lower portions of the lead frame conductors. Solder balls on the top of one integrated circuit package may be connected to mating solder balls on the bottom of another integrated circuit package, and so on, thereby achieving multiple stacking of integrated circuit packages.

Abstract: The present invention includes a Chien search device that implements an error-locator polynomial divided by a factor. The device includes first and second devices to generate .alpha..sup.i and .alpha..sup.-i, respectively. The device also includes a root determination block coupled to receive .alpha..sup.i and .alpha..sup.-i to provide a signal responsive to .alpha..sup.-i. In particular, the signal represents that .alpha..sup.-i is a root of the error-locator polynomial. The root determination block includes multiple root determination circuits to find the roots of the error-locator polynomial for each data interleave.

Abstract: A method for simulating an integrated circuit design that automatically generates an interface between a test bench and a device design for simulation. The method determines that the signal format and timing information of the test bench conforms to the constraints of some target ATE. If the information conforms, an array of buffers is created to provide the interface. Each of the buffers are defined according to the signal timing information. The interface is then incorporated into a test bench stimuli generator and the design is simulated. In this manner, the method allows for the generation of a simulation that can be then reproduced on any target ATE.

Abstract: A system for providing an optimal cluster of cells on the surface of a semiconductor chip is provided herein. The system collects a predetermined quantity of cells, this predetermined quantity containing a center cell, and all cells are assigned a distance value from the center cell. A coordinate is assigned to each cell based on its associated distance value, and new cell positions are calculated based on related cell positions and weights associated with each cell.

Abstract: A data frame synchronizer identifies frame boundaries in a serial data stream formed of a set of multi-bit frames. Selected frames in the set have a frame boundary bit at a specified location within the frame, and the frame boundary bits together form a predetermined pattern. The frame synchronizer includes a memory array having a memory data input, a memory data output and a plurality of rows and columns for storing the serial data stream. A memory control circuit is coupled to the memory array for writing successive bits of the serial data stream into the memory array through the memory data input in a sequence such that all of the frame boundary bits align in one of the rows. As each bit is being written into the memory array, the memory control circuit reads the corresponding row through the data output. A pattern detector is coupled to the memory data output for comparing the row with a predetermined pattern.

Abstract: A semiconductor memory device is constituted such that, when a first wiring layer provides a bit line of a first common complementary data line pair and a third wiring layer provides a bit line of a second common complementary data line pair, a second wiring layer makes an overlapped area between the bit line and the bit bar line of the second common complementary dada line pair equal to the bit line of the first common complementary data line pair and also an overlapped area between the bit line and the bit bar line of the first common complementary data line pair equal to the bit line of the second common complementary data line pair.

Abstract: A method and apparatus for converting a layout design for the metallization layer integrated circuit pattern to a reticle design having corrections for depth of focus problems. The apparatus includes a design rule checker which is configured to identify locations of the layout design which are expected to produce narrowed regions of the image caused by depth of focus variations at intersections between defined line features of the layout design and the elevated portions of the topographical variations. A depth of focus correction unit is included which is adapted to modify the layout design for the metallization integrated circuit pattern at the locations by increasing the line width of the defined line features from the integrated circuit pattern to correct for these depth of focus problems.

Abstract: A shielding conductor is spaced from a matrix of memory cells in a dynamic random access memory (DRAM) to shield the memory cells from noise signals, such as the noise created by components of a system level integrated circuit (SLIC). The shielding conductor is connected to one of a reference or potential source, preferably external to the DRAM segment. The shielding conductor distributes the effect of noise and maintains a uniform reference potential with respect to the DRAM components with which it overlays or connects. The shielding conductor comprises a plurality of connected intersecting conductors which form a mesh which overlays substantially the entire matrix. The mesh is connected to components, such as an isolating well or a capacitor reference potential conductor, at a plurality of spaced-apart locations over the entire matrix. The shielding conductor may also be a single integral conductor which overlays the entire matrix, including the bit and word lines.

Abstract: The invention provides a method and apparatus for increasing the efficiency of data transfer between a host computer and a disk array in a RAID system. The invention operates by splitting up large I/O requests from the computer into smaller, more manageable pieces and processing the pieces as though they were individual I/O requests. In one embodiment, the invention keeps only a limited number of these smaller individual I/O requests "active" at any particular time so that a single large I/O request cannot preclude other I/O requests from making progress in the controller. Both the size of the smaller I/O request pieces and the limited number of these pieces which will be "active" at any one time may be tunable parameters. The invention improves the efficiency of data transfer between the host computer and the array of disk drives by providing for increased overlap of activity in the controller. This increased overlap of activity results in increased controller throughput.