Abstract: An add with circular mask operation is executed in a RISC processor which includes a coprocessor having a register for storing a circular mask value. A circular mask instruction to the coprocessor includes a value in an immediate field and identifies a general register (RS), and a destination register (RT). The coprocessor operates on the value stored in the general register with the value in the immediate field and then masks the results using the circular mask value. The results are then stored in the destination register. The operation includes sign-extending the immediate field before adding to the contents of the general register to provide a sum, and the sum is then masked with the circular mask value.

Abstract: A method is provided for forming planar, self-aligned spaced-apart wells without a high temperature oxidation step to form an ion barrier. The method comprises preparing a substrate with a silicon dioxide-polysilicon-silicon dioxide barrier layer that can be etched to expose different sublayers of the barrier at selected junctures in the production process. A single masking step defines the location of a first set of wells on the prepared substrate. The outer silicon dioxide layer is etched to expose the polysilicon layer at the selected locations, and the substrate is implanted to form the first set of wells. Following ion implantation, the substrate photo-resist is removed, and the substrate is exposed to a germanium-silicon mixture under conditions selected to preferentially deposit a germanium-silicon alloy barrier layer on the exposed polysilicon layer.

Abstract: One or two, or more, additional conductive layers, separated from one another (if two or more) and separated from a patterned (signal) conductive layer are formed in a flexible substrate, for mounting a semiconductor die in a semiconductor device assembly. These additional layers are used as separate planes for carrying power and/or ground from outside the assembly to the die, on a separate plane from signals entering or exiting the die. TAB processes are disclosed for cutting, bending and bonding inner and outer portions of selected signal layer traces to respective inner and outer edge portions of the additional conductive layer(s), including a two-stage process of (1) first cutting, bending and tacking the selected traces to the additional layer(s), and then (2) repositioning a bonding tool and securely bonding the selected traces to the additional layer(s). A tool (die pedestal) for aiding in the assembly process is also disclosed.

Abstract: This invention relates to an improved memory storage system which allows interleaving between two separate memory banks. In this way, data can be retrieved simultaneously from the two memory banks and placed on the data bus alternately. While the data from one data bank is on the data bus, data is being retrieved from the other data bank. In general, a data bank requires a number of wait states in order to retrieve data, during which no data is transferred onto the data bus from that particular data bank. However, by interleaving the data between two separate memory banks, data retrieved from the first memory bank can be placed on the data bus while the second memory bank is undergoing several wait states retrieving the next group of data. In this way, data is continuously placed on the data bus and the number of wait states during which no data is present on the data bus are decreased, preferably to zero.

Abstract: A built-in self-repair system includes an on-chip clock generator for triggering the repairing process to repair defective memory lines or blocks in a memory array of an ASIC chip. The on-chip clock generator enables the self-repair process to start at the power up of a computer system without a need for an external test-triggering signal. The system includes a built-in self-test circuit that tests for a defective row memory line or a defective I/O memory block. The system further includes a fault-latching-and repair-execution circuit that repairs a row memory line or an I/O memory block. Repairing an IO memory block effectively repairs faults that occur between any two adjacent column shorts within an IO memory block. The preferred repairing scheme adopts a 15N diagnosis to achieve high fault correction so that a large percentage of defective memory cells can be replaced by redundant row memory lines or redundant I/O memory blocks.

Abstract: A generalized data processing path including memory, select logic, adders, subtractors, multipliers, and accumulators (MACs) is organized to perform discrete cosine transforms (DCT), quantization, inverse DCT and inverse quantization operations desired for a video motion compensation system. The select logic selects or bypasses particular adders and subtractors on the front and rear end of the data path depending upon whether the particular operation requires a butterfly operation. A plurality of adders, subtractors and MACs enable data values to be calculated in parallel for efficiency. Control logic is provided to control the memory, select logic and MACs to control data flow and the particular operation being performed. The control logic preferably includes a microcontroller, a microprocessor or associated coprocessor, etc., or a combination of these various types of controllers and processors.

Abstract: A plurality of processors which can be the same or different are formed on a single integrated circuit chip together with a memory controller and an I/O controller, and are interconnected by a data transfer bus. The processors can have larger word lengths and operate at higher speeds than comparable single chip processors due to reduced latency and signal path lengths. The processors are further interconnected by a processor synchronization bus which enables one processor to cause another processor to perform a task by generating an interrupt and passing the required parameters. The parameters can be passed via shared memory, or via a bidirectional data section of the processor synchronization bus. A processor running a large scale CAD or similar application can cause a smaller processor to perform I/O tasks in native code.

Abstract: An electronic camera includes a photosensor array that is supported by a housing. The photosensor array includes a plurality of binary diffractive lens elements for forming a substantially identical light image on laterally spaced areas of a surface respectively. A plurality of photosensors are disposed on the surface within the laterally spaced areas for receiving different portions of the light image respectively such that the photosensors in aggregation receive substantially all of the light image. The photosensors can have constant spacings therebetween, and the lenses have spacings therebetween that increase away from a predetermined point in the array. Alternatively, the lenses can have constant spacings therebetween, and the photosensors have spacings therebetween that increase away from a predetermined point in the array.

Abstract: An anisotropic etching process is disclosed in which two sources of process gas are provided to a plasma reactor having at least three electrodes. In a plasma, the first process gas provides etchant species which are reactive with a substrate and the second process gas provides barrier species which protect trench sidewalls from reaction with the etchant species. For etching silicon, the first process gas may be chlorine, chloro-trifluoromethane, oxygen, etc., and the second process gas may be C.sub.2 F.sub.6, SF.sub.6, BCl.sub.3, or other compound that either combines with etchant species on a trench sidewall or forms a protective polymer film on such trench sidewall. A disclosed plasma reactor includes a grounded first electrode which forms part of the reactor's enclosure, a coiled second electrode disposed above and separated from the reactor enclosure by a dielectric shield, and a planar third electrode located below the substrate to be etched.

Abstract: A system and process which enables storage of more than two logic states in a memory cell. In one embodiment, a programmable resistor is coupled in series with a transistor between a supply voltage and a data read line. When an access signal is asserted, the transistor provides a conductive path, and a voltage drop is sustained by the programmable resistor. The programmable resistor has a resistance which is set during a programming step to one of a plurality of values by passing a heating current through the programmable resistor for one of a corresponding plurality of predetermined lengths of time. When the access signal is asserted, the voltage drop sustained across the programmable resistor is indicative of the stored logic state. An analog-to-digital (A/D) converter is coupled to the data read line so as to sense the voltage drop and determine the state represented.

Abstract: A control system operates in a pipelined mode for executing multiple clock cycle instructions and in an open loop mode for executing single clock cycle instructions. A plurality of electrical functional units are capable of executing single clock cycle instructions and multiple clock cycle instructions that are individually addressed and applied thereto by a processor. The functional units generate current operational statuses after each clock cycle. A status indicator applies new operational statuses of the functional units to the processor. A status memory stores previous operational statuses of the functional units. A control unit controls the status indicator to apply the previous operational statuses to the processor as the new operational statuses after one of the single clock cycle instructions has been applied to the functional units.

Abstract: A decoder de-interleaver comprises a de-interleaver for de-interleaving received interleaved encoded data that includes periodic decoder synchronization signals to produce de-interleaved encoded data. A decoder decodes the de-interleaved encoded data to produce output data. The de-interleaver has a latency such that the de-interleaved encoded data is delayed by (B-1) times a period of the decoder synchronization signals plus a constant interval, where B is the interleave depth. A synchronization pulse generator receives the interleaved and encoded data and generates decoder synchronization pulses that are substantially coincident with the decoder synchronization signals. A delay unit is connected between the synchronization pulse generator and the decoder for delaying the decoder synchronization pulses by the constant interval. The decoder thereby receives decoder synchronization pulses that correspond to previous decoder synchronization signals, but functions properly because the relative timing is correct.

Abstract: A gate array masterslice having a minimal input/output slot and variable pad pitch architecture is disclosed. In the masterslice, many identical input/output slots ring the periphery of a semiconductor substrate and contain only the special devices necessary for input/output circuits. Each of the input/output slots include (i) a first region containing a plurality of tuning transistors of different sizes, (ii) a second region having one or more PMOS transistors, each of a size greater than any one of the plurality of tuning transistors, (iii) a third region having one or more NMOS transistors, each of a size greater than any one of the plurality of tuning transistors, and (iv) a fourth region containing one or more devices for providing electrostatic discharge protection. One to four PMOS transistors are provided in the second slot region and one to four NMOS transistors are provided in the third slot region.

Abstract: According to the present invention, a method is provided for attaching a package substrate to a circuit board. In one version of the invention, the package substrate has a semiconductor die disposed thereon, and the semiconductor die has a plurality of bond pads formed thereon which are electrically connected to conductive traces on the package substrate. In one embodiment of the invention, the method comprises the steps of attaching a first surface of an electrical connector to one of the conductive traces by thermoplastic adhesion; and attaching a second surface of the electrical connector to a conducting pad on the circuit board, also by thermoplastic adhesion.

Abstract: A process for forming an integrated circuit structure is described wherein individual integrated circuit devices such as MOS or bipolar transistors are constructed on and in a semiconductor substrate and one or more layers of metal interconnects are constructed on and in a second substrate, preferably of similar thickness, and the two substrates are then aligned and bonded together to thereby provide electrical interconnections of individual integrated circuit devices on the semiconductor substrate with appropriate metal interconnects on the second substrate to provide the desired integrated circuit structure.

Abstract: Rapid Thermal Processing of a semiconductor wafer is performed by scanning a laser beam across a silicon dioxide film in contact with a surface of the wafer. The silicon dioxide film absorbs the energy from the laser beam and converts the energy to heat. The heat, in turn, is transferred to the wafer. Temperature feedback can be obtained to increase control and uniformity of temperatures across the wafer.

Abstract: A differential delay buffer includes a variable delay buffer unit, the variable delay buffer unit having a differential stage followed by a variable hysteresis stage. A plurality of variable delay buffer units can be cascaded together, in each variable delay buffer units a part of the required delay being effected. The variable hysteresis stage is responsive to the signal level at a second differential stage output to recover the signal at a first differential signal output from the variable delay buffer unit and is responsive to the signal level at a first differential stage output to recover the signal at the second delayed differential signal output for the variable delay buffer unit. The differential delay buffer can be included in a delay locked loop in data transmission applications.

Abstract: A surface-mount ball-grid array package is provided for an integrated circuit assembly. The ball-grid array package has a circuit chip recess through which vias extend to open on a bottom surface of the package. A peripheral portion of the package is defined around the vias formed in the recess, and an integrated circuit die is seated within this peripheral portion. During manufacture, the package is held on a vacuum chuck by applying vacuum to the peripheral portion of the package. An adhesive material is placed in the recess to extend partially through the vias. The circuit chip is thereafter disposed in the recess on the adhesive material to complete the fabrication process. Ambient air is communicated to the vias on the bottom surface of the package to prevent the adhesive from being pulled through the vias by the applied vacuum.

Abstract: A method of cell placement for an integrated circuit chip includes performing a contraction operation by which at least some of the cells are relocated to new positions that provide lower interconnect wirelength. For each cell, the centroid of the net of cells to which the cell is connected is computed. The cell is then moved toward the centroid by a distance that is equal to the distance from the current position of the cell to the centroid multiplied by a "chaos" factor. This process continues until a specific energy condition is met; then the `expansion` mode is entered. An expansion operation is then performed by which the net force exerted on each cell by other cells in the placement and a resulting altered velocity of the cell are calculated, and a new cell position is calculated based on the altered velocity over an incremental length of time. The system stays in expansion mode until another energy criterion is met.

Abstract: Electronic systems utilizing a plurality of integrated circuit packages having at least some large gaps between edges of a semiconductor die and the inner ends of package conductors defining a die-receiving area, one or more bond wire support structure are disposed in the gap, thereby causing a long bond wire to behave as two or more shorter bond wires. The bond wires are tacked to a top surface of the support structure by various alternative means. Alternatively, a "jumper" structure having conductive traces of graduated length can be disposed in the die-receiving area between the die and the edges of the die-receiving area, providing an intermediate connection between the die and the leads of the package, thereby permitting short bond wires to be used in lieu of long bond wires.