Abstract: Disclosed herein is a multi-clock interface, an integrated circuit and a module thereof having the multi-clock interface and a library having cells corresponding to the above noted circuitry. In one embodiment the multi-clock interface includes: (1) a multi-clock reset synchronizer configured to receive a first external clock signal and a second external clock signal that is a multiple of the first clock signal, the reset synchronizer configured to synchronize a reset of both the first and second external clock signals and based thereon generate a reset release signal and (2) a multi-phase clock generator configured to receive the reset release signal and the second clock signal, the multi-phase clock generator configured to generate multiple clock phases from the second clock signal based on the reset release signal.

Abstract: Various embodiments of the present invention provide single-ended and differential current drivers for heat assisted magnetic recording and other applications. For example, a current driver is disclosed that includes an upper output terminal and lower output terminal, a number of current switches operable to selectively contribute electrical currents through the upper and lower output terminals, a control input for each of the current switches operable to control the electrical currents, and a voltage supply operable to establish a voltage across the upper and output terminals.

Abstract: Various embodiments of the present invention provide systems and methods for data writing. As an example, a heat assisted loopback circuit is discussed that includes: a read circuit, a magnetic write circuit, a heat write circuit, and a loopback circuit. The read circuit is operable to sense data from a storage medium, and to provide the sensed data as a read output. The magnetic write circuit is operable to provide a write output corresponding to an excitation signal of a write head. The heat write circuit is operable to provide a heat output corresponding to an excitation signal of a heat source. The loopback circuit is operable to selectively couple a derivative of the heat output to the read output and to selectively couple a derivative of the write output to the read output.

Abstract: A method is disclosed for updating parity information in a RAID 6 system wherein only one parity block is read during each write operation. Both parity blocks may be updated from the new data, the data being overwritten and either of the old blocks of parity information. A method for load balancing in a RAID 6 system using this method is also disclosed.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for detecting patterns in a data stream.

Abstract: A method includes applying a write Input/Output (I/O) queue interval to a Logical Unit (LU) member of a consistency group (CG). The method also includes marking each write I/O with a timestamp and suspending I/O from the participating storage array to the LU member of the CG upon the participating storage array receiving a snapshot request from a master storage array. The method further includes determining whether the snapshot request timestamp is within the write I/O queue interval of the participating storage array.

Abstract: In one embodiment, a scheme for reliably reading data values, such as rapidly-changing counter values, from a memory location. Instead of performing a single read operation, a set of N consecutive read operations is performed to obtain a set of N samples. Since, for counter values and the like, the frequency of occurrence of out-of-sequence values is relatively low, it is expected that a majority of the N samples will be in sequence. Of these N samples, the largest subset of monotonically-increasing values is selected. The median value of this subset of monotonically non-decreasing values is returned as a reliable result of the read operation.

Abstract: The invention provides for SSD cache expansion by assigning all excess overprovisioned space (OP) above a level of advertised SSD memory to SSD cache. As additional SSD memory is needed to provide the advertised SSD memory, an offsetting portion of the OP is reassigned from excess overprovisioned space to the SSD cache. In this manner, the advertised SSD memory is maintained while continuously allocating all available excess OP to cache. The result is that all of the available SSD memory is allocated to cache, a portion to maintain the advertised SSD memory and the balance as excess OP allocated to cache. This eliminates idle OP in the SSD allocation.

Abstract: Methods and structure for transferring administrative information through a communication interface. Features and aspects hereof provide for exchanging administrative information between an initiator device and a target device using read and write commands encoded with a reserved sub-tag value. In the context of a Serial Advanced Technology Attachment (SATA) system, a portion of a parameter (e.g., the LBA parameter) of a read or write command (a Native Command Queuing command) is defined to encode a sub-tag value. One or more sub-tag values are reserved to indicate that the corresponding read or write command is related to the exchange of administrative information rather than the reading or writing of data on a storage device. A parameter value encoded in the LBA field or data length field of the read or write command indicates administrative data to be returned to the initiator or to be updated within the target device.

Abstract: A hard disk drive or other disk-based storage device comprises a storage disk, a write head configured to write data to the disk, and control circuitry coupled to the write head. The control circuitry comprises a write driver and degauss circuitry associated with the write driver. The degauss circuitry is configured to control a degauss signal waveform to be applied to the write head by the write driver, and comprises separate amplitude envelope control mechanisms for steady state and overshoot portions of the degauss signal waveform. The separate amplitude envelope control mechanisms may comprise, for example, separate steady state and overshoot controllers for controlling the amplitude envelope decay rates of the respective steady state and overshoot portions of the degauss signal waveform over the plurality of pulses.

Abstract: Methods and structure for transferring additional parameters through a communication interface with limited parameter passing features. Features and aspects hereof provide for generating and transmitting multiple related commands from an initiator device to a target device where one or more initial commands provide additional parameters. The additional parameters are utilized in processing the last of the multiple commands to actually perform a desired data transfer. The initial commands and the data transfer command may all be associated by encoding of a common tag or sub-tag value in each command. The initial commands may be read/write commands having a zero data transfer length. The associated data transfer command may be a read/write command having a non-zero data transfer length. The initial commands each provide one or more additional parameters for processing the data transfer command in addition to the standard parameters that may be encoded in the data transfer command.

Abstract: An integrated circuit comprises a memory or other type of circuit core having an input interface and an output interface, built-in self-test circuitry configured for testing of the circuit core between its input and output interfaces in a built-in self-test mode of operation, and at least one scan chain having a plurality of scan cells. The scan cells of the scan chain are coupled to respective signal lines at the input and output interfaces and configured to allow capture of functional signal values from those signal lines in a functional mode of operation and shifting out of the captured functional signal values in a scan shift mode of operation. This allows detection of faults associated with functional paths of the interface that would otherwise not be detectable using the built-in self-test circuitry.

Abstract: A memory device includes a memory array comprising a plurality of memory cells. At least one of the memory cells comprises a pair of cross-coupled inverters, and a plurality of ports, including at least one write port. A given write port comprises at least one drive control circuit having an output coupled to respective gate terminals of both a write assist transistor and a drive transistor, with the write assist transistor being arranged in series with one of a pull-up and a pull-down path of a corresponding one of the inverters, and the drive transistor being configured to hold one of the internal nodes at a designated logic level in conjunction with a write operation. First and second drive control circuits of this type may generate complementary control signals for application to respective pairs of write assist and drive transistors associated with respective ones of the inverters.

Abstract: Methods and systems for executing a decompressed portion of an option memory in a shadow memory. An area of system memory is allocated and a portion of the option memory is decompressed using the allocated area. The decompressed portion is stored in the shadow memory so the decompressed portion can be executed in shadow memory.

Abstract: Various embodiments of the present invention provide systems and methods for data filter tuning. As an example, a method for filter tuning is disclosed that includes: providing a tunable filter having an operation filter and a calibration filter; applying a low frequency test input to the operation filter in place of an input signal to yield a first filter output; calculating a low frequency magnitude value corresponding to the first filter output; applying a high frequency test input to the operation filter in place of an input signal to yield a second filter output; calculating a high frequency magnitude value corresponding to the second filter output; modifying a tuning factor of the calibration filter when a ratio of the high frequency magnitude value and the low frequency magnitude value is outside of a defined range; and storing the tuning factor of the calibration filter when the ratio of the high frequency magnitude value and the low frequency magnitude value is within the defined range.

Abstract: Methods and systems for advanced interrupt processing and scheduling are provided. The system comprises a memory operable to store interrupt priorities, an interface, and a processor operable to acquire incoming interrupts and to handle the incoming interrupts according to the interrupt priorities. The processor is also operable to receive interrupt processing criteria from the interface (sent, for example, from a device not directly coupled with the system), and to modify the interrupt priorities of the memory based upon the interrupt processing criteria without losing incoming processing requests for the system. Additionally, the processor is operable to process the incoming interrupts according to the modified interrupt priorities responsive to modifying the interrupt priorities.

Abstract: Various embodiments of the present invention provide systems and methods for generating a code format. One method discussed includes: Various embodiments of the present invention provide methods for generating a code format. Such methods include: receiving an indication of a low weight codeword having a trapping set; selecting an initial value for a base matrix; testing the low weight codeword after modification by the initial value to determine an updated weight of the low weight codeword; and testing the low weight codeword after modification by the initial value to determine whether the trapping set remains.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. A data processing circuit is disclosed that includes: a data detector circuit, a first symbol constrained arrangement circuit, and a second symbol constrained arrangement circuit. The data detector circuit is operable to apply a data detection algorithm to a combination of a first input data set and a decoded data set to yield a detected output that includes a number of non-binary symbols. The first symbol constrained arrangement circuit is operable to receive the detected output and to re-arrange the detected output in accordance with a first arrangement algorithm to yield a re-arranged output. The bits for at least one non-binary symbol from the detected output are maintained together in the re-arranged output.

Abstract: Various embodiments of the present invention provide systems, methods and circuits for use of a memory system. As one example, an electronics system is disclosed that includes a memory bank, a memory access controller circuit, and an encoding circuit. The memory bank includes a plurality of multi-bit memory cells that each is operable to hold at least two bits. The memory access controller circuit is operable to determine a use frequency of a data set maintained in the memory bank. The encoding circuit is operable to encode the data set to yield an encoded output for writing to the memory bank. The encoding level for the data set is selected based at least in part on the use frequency of the data set.

Abstract: Techniques are disclosed for asynchronous calibration for eye diagram generation. For example, a method for calibrating a process for generating a data eye associated with a received signal comprises the following steps. Samples of the received signal are obtained for a first unit interval using a first data latch and a roaming latch. A delay offset is determined between the first data latch and the roaming latch by comparing at least one sample obtained using the first data latch and at least one sample obtained using the roaming latch, wherein the delay offset determined by the comparison is used to calibrate the process for generating the data eye associated with the received signal. A similar comparison may be done for a second data latch and used to calibrate the process. The method is able to find the accurate position of each data latch with respect to the roaming latch so as to improve the accuracy of data decoding in a digital receiver, i.e., provide receiver optimization.