Abstract: A lighting apparatus having a base member and a directional member are shown and described. The base member includes a first surface having a plurality of reflective elements extending therefrom. The base member also including a plurality of openings arranged in a pattern. Each openings is configured to receive a respective light source. The directional member has a portion of a reflective surface positioned relative to at least one opening to reflect light radiating from a lighting source disposed within the opening towards a portion of at least one of the reflective elements extending from the base member.

Abstract: A method for designing an integrated circuit is disclosed. The method generally comprises the steps of (A) splitting a design layout of the integrated circuit into a plurality of tiles, (B) adding a plurality of tie-to cells to the design layout, wherein at least one of the tie-to cells generating a tie-to signal at a particular logical level is added into each of the tiles having at least one gate with an input fixed to the particular logical level and (C) routing the tie-to signal to each of the inputs within each of the tiles.

Abstract: A semiconductor platform for implementing multiple-frequency operations includes multiple physical resources comprising embedded functions and a configurable transistor fabric. The transistor fabric includes at least first and second portions, the first portion being programmable to instantiate a first function having higher frequency operations than the second portion. The platform further includes multiple logical resources corresponding to the physical resources of the semiconductor platform and a configurable power mesh to support multiple frequency operations configurable from the transistor fabric. The power mesh includes at least first and second configurable grids. The first configurable grid is operable at a different frequency than the second configurable grid. The power mesh is modifiable, as a function of a desired performance of a customer's requirements, in a vicinity of the first portion of the configurable transistor fabric to support the first function having higher frequency operations.

Abstract: A lighting device having a support module supporting LEDs and having an outer perimeter defining a curved portion, and a housing with an inner surface having a curved portion configured to receive the curved portion of the support module to enable the disk to be aimed, while the curved portions of the disk and housing remain in contact. Optional adjustment means facilitate aiming of the support module without the need to open the sealed LED module.

Abstract: Disclosed is a method and SAS controller that abstract access from virtual machines operating on a host system to SAS physical devices connected to the SAS controller without a routing table for port-to-port messaging on the SAS controller. An embodiment may create a virtual expander for each physical port of the SAS controller and further create virtual ports within the virtual expanders to provide abstracted access to SAS physical devices for the virtual machines. The SAS physical devices may be replicated/cloned within the virtual ports. Each replicated/cloned SAS physical device may be assigned a unique SAS address for the SAS controller. If a physical expander that supports zoning is connected to a SAS controller port, an embodiment may further selectively replicate/clone the SAS physical devices for a virtual port based on whether or not a SAS physical device is included in a zoning group associated with the virtual port.

Abstract: Methods and structure for masking of logical unit numbers (LUNs) within a switching device coupled with one or more storage enclosures. Each storage enclosure defines one or more logical volumes each identified by a LUN within the storage enclosures. The switching device gathers LUN definition information regarding each LUN defined by each storage enclosure coupled with the switching device. LUN access permission information may be provided by an administrative node/user defining a level of access permitted or denied for each host system for each LUN for each storage enclosure. The switching device then intercepts a REPORT LUNS command from any host directed to a storage enclosure and responds with only those LUNs to which the requesting host system has permitted access. Further, any other SCSI command intercepted at the switching device directed to a LUN to which the host system does not have access is modified to identify an invalid LUN.

Abstract: In one embodiment, the invention is a method for performing preamble detection in a wireless communication network. The method performs a first dwell, wherein non-overlapping chunks of received data are processed to generate partial correlation values for each possible combination of a signature code and delay. Candidate selection is performed by comparing each of the partial correlation values to a candidate-selection threshold. For each detected candidate, the chunks of received data are processed to generate full correlation values. Each full correlation value is then compared to a preamble-detection threshold to detect a transmitted signature. Generating full correlation values for only the selected candidates reduces the computation complexity over prior-art methods that generate full correlation values for all signatures at all delays.

Abstract: A method of subtracting floating-point numbers includes determining whether a first sign associated with a first floating-point number is unequal to a second sign associated with a second floating-point number, determining whether a first exponent associated with the first floating-point number is less than a second exponent associated with the second floating-point number, negating a first mantissa associated with the first floating-point number when the first sign is unequal to the second sign and determining that the first exponent is less than the second exponent, and adding the first mantissa to a second mantissa associated with the second floating-point number when the first sign is unequal to the second sign and determining that the first exponent is less than the second exponent. Embodiments of a corresponding computer-readable medium and device are also provided.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes an equalizer circuit, a noise predictive filter circuit, a data detector circuit, a data reconstruction circuit, and an adaptation circuit. The equalizer circuit is operable to receive a data input and to provide an equalized output based at least in part on an equalizer coefficient. The noise predictive filter circuit is operable to receive the equalized output and to provide a noise whitened output based at least in part on a noise predictive filter coefficient. The data detector circuit is operable to apply a data detection algorithm to the noise whitened output to yield a detected output. The data reconstruction circuit is operable to receive the detected output and to provide a reconstructed output corresponding to the equalized output based at least in part on a target polynomial.

Abstract: Disclosed is a system and method that resolves a mismatch between software versions executing on redundant controllers. A mismatch between a first software version executing on a first redundant controller and a second software version executing on a second redundant controller is identified. By comparing software version identifiers associated with the first software version, the second software version, and a stored system software identifier, a preferred software version is selected. The preferred software version is copied from a controller running the preferred software version to the other controllers.

Abstract: Systems and methods for management of replicated storage. Features and aspects hereof provide management of data replication among a plurality of storage systems in a manner substantially transparent to host systems attached to the storage systems. The storage systems are coupled to one another through a replication link. One storage systems is designated the primary storage system and all others are designated secondary storage systems. A common logical volume is defined with a common logical volume device identifier used by all of the replicating storage systems of a replication group and their respective attached host systems. The primary storage system processes I/O requests directed to the logical volume by accessing its physical storage volume and forwarding the request to be replicated to all secondary storage systems over the replication link. Secondary storage systems process I/O requests by shipping them over the replication link to the primary storage system for processing.

Abstract: Various embodiments of the present invention provide systems and methods for min-sum based decoding of non-binary LDPC codes. For example, a non-binary low density parity check data decoding system is discussed that includes a variable node processor and a check node processor. The variable node processor is operable to generate variable node to check node message vectors and to calculate perceived values based on check node to variable node message vectors. The check node processor is operable to generate the check node to variable node message vectors and to calculate checksums based on variable node to check node message vectors. The check node processor includes a minimum and subminimum finder circuit operable to process a plurality of sub-messages in each variable node to check node message vector. The check node processor also includes a select and combine circuit operable to combine an output of the minimum and subminimum finder circuit to generate the check node to variable node message vectors.

Abstract: Various embodiments of the present invention provide systems and methods for sequence detection. As an example, a method for data detection is disclosed that includes: receiving a series of data samples at a detector circuit; multiplying a portion of the series of data samples by a first correlator value corresponding to a first binary transition to yield a first value; multiplying the portion of the series of data samples by a second correlator value corresponding to a second binary transition to yield a second value; adding the first value to a prior state value to yield a first interim value; adding the second value to the prior state value to yield a second interim value; and selecting the larger of the first interim value and the second interim value to yield a surviving interim value.

Abstract: Various embodiments of the present invention provide systems and methods for sync mark detection. As an example, a sync mark detection circuit is discussed that includes a storage circuit, a plurality of noise predictive filter circuits, and a controller circuit. The storage circuit is operable to store a data input as a stored input. The plurality of noise predictive filters are operable to receive a processing input. At least one of the noise predictive filters is selectably modifiable to either increase the probability of finding a sync mark in the processing input or to maintain a baseline probability of finding the sync mark in the processing input. The controller circuit is operable to determine an operational mode that may be a standard operational mode, a bit flipping mode, or a filter modification mode.

Abstract: Various embodiments of the present invention provide systems and methods for generating a code format. One method discussed includes: receiving a first matrix having a row width and a column height that is greater than one; incorporating a circulant into a first column of the first matrix; testing the first column for trapping sets, wherein at least one trapping set is identified; selecting a value to mitigate the identified trapping set; and augmenting the first matrix with a second matrix to yield a composite matrix. The second matrix has the selected value in the first column, and wherein the identified trapping set is mitigated.

Abstract: A method for computing and storing parity information in a RAID system includes dividing each segment in a stripe into a data block and a parity block, and storing in each parity block, parity information for a limited number of other data blocks in the stripe. A method for rebuilding data in a RAID system includes rebuilding the data from parity information and storing the rebuilt data on reserve portions of the remaining disks in the system.

Abstract: A SAS expander collects data access information associated with a nexus and determines whether a data prefetch is appropriate. The SAS expander identifies potential data blocks utilizing previous data requests of the nexus. The SAS expander issues a data request to the target for the potential data blocks. The SAS expander stores the potential data blocks within a prefetch cache for future utilization within a data read.

Abstract: A method and apparatus are provided for using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are also defined. Timing characteristics of each tiling variant of each characterization memory are stored in the memory timing database for the memory resource based on sets of input ramptimes and output loads.

Abstract: Described embodiments schedule packets for transmission by a network processor. A traffic manager generates a scheduling hierarchy having a root scheduler and N levels. The network processor generates tasks corresponding to received packets. The traffic manager enqueues tasks in an associated queue. The queue has a corresponding level M, with a corresponding parent scheduler at each of M?1 levels in the scheduling hierarchy, where M is less than or equal to N. In a single scheduling cycle, a parent scheduler selects a child node to transmit one or more tasks, and the child node responds whether the scheduling is accepted, and if so, with a number of tasks for scheduling. Starting at the parent scheduler and iteratively repeating at each level until reaching the root scheduler, statistics corresponding to the selected node are updated. Output packets corresponding to the scheduled tasks are transmitted, thereby achieving a superscalar task scheduling throughput.

Abstract: Disclosed herein is a multi-clock interface, an integrated circuit and a module thereof having the multi-clock interface and a library having cells corresponding to the above noted circuitry. In one embodiment the multi-clock interface includes: (1) a multi-clock reset synchronizer configured to receive a first external clock signal and a second external clock signal that is a multiple of the first clock signal, the reset synchronizer configured to synchronize a reset of both the first and second external clock signals and based thereon generate a reset release signal and (2) a multi-phase clock generator configured to receive the reset release signal and the second clock signal, the multi-phase clock generator configured to generate multiple clock phases from the second clock signal based on the reset release signal.