Abstract: A lighting apparatus comprising a first lighting assembly comprising at least one lower light source configured to cast light over at least a near field and a second lighting assembly comprising at least one upper light source configured to cast light over at least a far field, the second lighting assembly mounted above the first lighting assembly.

Abstract: A static memory system with multiple memory cell that, in response to a reset signal, simultaneously resets or clears a segment of the memory cells in the memory. Clearing the entire memory or a portion thereof is accomplished by sequencing though a subset of address bits while asserting the reset signal.

Abstract: A method of reducing total power dissipation for logic cells includes selecting a distribution of logic cells corresponding to at least one path, computing a dynamic to static power ratio for each logic cell in the distribution of logic cells and ranking the dynamic to static power ratio for each logic cell into a lower group, a middle group and an upper group of logic cells. Additionally, the method includes swapping the lower group of logic cells and the upper group of logic cells for a reconfigured middle group of logic cells and verifying path timing for the reconfigured middle group of logic cells. Methods of reducing total power dissipation using Boolean equations and for logic cell sets are also provided.

Abstract: An apparatus including a bang-bang clock and data recovery module and a decision feedback equalizer. The decision feedback equalizer is coupled with the bang-bang clock and data recovery module. The apparatus is configured to reduce an effect on a settling point of the bang-bang clock and data recovery module due to coupling between the bang-bang clock and data recovery module and the decision feedback equalizer.

Abstract: In one embodiment, a multistage interconnection network (MIN) has two or more configurable stages, each stage having a plurality of switches. The network has one or more unused input terminals, each mapped using fixed switch connections to an unused output terminal. The network also has a set of used input terminals that are selectively mapped to a set of used output terminals based on values of control signals supplied to the stages. Each stage receives a different control signal, and each control signal is generated by cyclically shifting a control seed by a corresponding cyclic-shift value. Fixing the mappings of the unused terminals ensures that the used input terminals are not mapped to any unused output terminals. By storing only the control seed, memory requirements are reduced over networks that explicitly store individual control signals for all of the stages.

Abstract: A method for broadcast forwarding in a SAS topology having a zoned portion of a service delivery system (ZPSDS) is disclosed. The ZPSDS includes at least a first zoning expander and a second zoning expander. The method includes originating a broadcast primitive on the first zoning expander; forwarding solely the broadcast primitive to the second zoning expander from the first zoning expander; initiating a discovery process from the second zoning expander upon receiving the broadcast primitive; and generating a source zone group list upon completion of the discovery process.

Abstract: Methods and structure are provided for managing a Serial Attached SCSI (SAS) domain via Universal Serial Bus (USB) communications. The system comprises a SAS expander. The SAS expander comprises a plurality of physical links, a USB interface, and a control unit. The control unit is operable to receive USB packets via the USB interface, to determine SAS management information based upon the received USB packets, and to alter a configuration of the SAS domain based upon the SAS management information determined from the USB packets.

Abstract: Methods and structure for dynamically modifying SAS Zoning Features of a SAS expander based on present operating status of the expander. Rules are provided and interpreted within the expander to define changes to be made to the present SAS Zoning Features based on changes to the present operating status of the expander. The present operating status may be, for example, the present day, date, time of day, etc. Exemplary rules may define a modification to the zone group identifier to be associated with a PHY of the expander based on the present operating status of the expander. Exemplary rules may also define a modification to the zone permission defined for a pair of zone group identifiers. Further features and aspects hereof provide for a read-only zone permission value in addition the standards of the SAS specification.

Abstract: An integrated circuit (IC) or a block of an IC is routed. The signals of the netlist to be routed are grouped according the signal properties. A signal property may be the time or clock used to initiate the switching of the signal. The signals of each group are routed successively. This causes the signals of later groups to be routed between the signals of previous groups thereby providing shielding between signals lines of the same group.

Abstract: Described embodiments provide a method of transferring data from host devices to a media controller. The media controller generates a transfer context for each write request received from a host device. Receive-data threads corresponding to data transfer contexts for each transfer context are generated, each receive-data thread corresponding to a data transfer between a host device and the media controller. Buffer threads corresponding to data transfer contexts for each transfer context are generated, each buffer thread corresponding to a data transfer between the receive data path and a buffer subsystem. The receive-data and buffer threads are tracked for each transfer context. For each tracked transfer context, data from the receive datapath is iteratively transferred to the buffer subsystem for a previous data transfer context of the buffer thread while data from the host device is transferred to the receive datapath for a subsequent data transfer context of the receive-data thread.

Abstract: In described embodiments, a Floating Tap, Feed Forward Equalizer (FT-FFE) achieves performance comparable to a full size, long FFE when equalizing wire line channels in, for example, SerDes receivers. A FT-FFE might be employed as a standalone datapath equalizer, or might be employed in conjunction with other equalization techniques.

Abstract: An illumination device comprises a plurality of light sources, light sequencing circuitry coupled to the light sources, a light guide structure for directing light from the plurality of light sources over a surface of a display screen to be illuminated, and a user interface for providing control input to the light sequencing circuitry. The light sequencing circuitry comprises a logic state machine responsive to the control input to select one of a plurality of available sequencing modes for the plurality of light sources, a code generator operative to generate output signals controlling respective ones of the light sources responsive to the selected one of the sequencing modes, and timing circuitry for defining timing intervals for processing of the control input by the logic state machine to determine the selected one of the sequencing modes and for generation of the corresponding output signals by the code generator.

Abstract: A system and method for optimizing slave transaction ID width based on sparse connection between multiple masters and multiple slaves in a multilayer multilevel interconnect system-on-chip (SOC) architecture are disclosed. In one embodiment, slave transaction ID widths are computed for a first processing subsystem and a second processing subsystem including multiple masters and multiple slaves. Further, a slave transaction ID for each master to any slave in the first processing subsystem and in the second processing subsystem is generated based on the computed slave transaction ID width. Furthermore, sparse connection information between the multiple masters and multiple slaves is determined via a first bus matrix in the first processing subsystem. A first optimized slave transaction ID for each master to any slave in the first processing subsystem is then generated by removing don't care bits in each generated slave transaction ID based on the sparse connection information.

Abstract: A method of forming an electronic device provides an electronic device substrate having a solder bump pad located thereover. A nickel-containing layer is located over the solder bump pad. A copper-containing layer is formed on the nickel-containing layer prior to subjecting the electronic device to a reflow process.

Abstract: Methods and structure for diagnosing errors in the initialization of DDR memory “on board” a storage controller or a storage expander are presented herein. The features and aspects discussed herein allow for the debugging of the DDR memory initialization. A memory diagnostic system is operable on a storage controller and includes an initialization module in communication with a firmware module of the storage controller. The memory diagnostic system is adapted to initialize a Double Date Rate (DDR) memory of the storage controller. The memory diagnostic system also includes an application programming interface adapted to retrieve initialization information from the initialization module and transfer the initialization information to a debug system via a direct communication link between the application programming interface and the debug system to diagnose the initialization of the DDR memory and to debug the initialization module based on the initialization information.

Abstract: A method is provided for performing caching in a processing system including at least one data cache. The method includes the steps of: determining whether each of at least a subset of cache entries stored in the data cache comprises data that has been loaded using fetch ahead (FA); associating an identifier with each cache entry in the subset of cache entries, the identifier indicating whether the cache entry comprises data that has been loaded using FA; and implementing a cache replacement policy for controlling replacement of at least a given cache entry in the data cache with a new cache entry as a function of the identifier associated with the given cache entry.

Abstract: An integrated circuit chip that supports stored-pattern (SP) logic built-in self-testing (LBIST) includes a device under test (DUT) and a test controller. System-level SP LBIST testing is performed using an external, system ATE (automated test equipment) that transmits test input data to the test controller for application to the DUT, which generates test output data that is transmitted from the test controller to the system ATE, which performs golden signature comparisons on the test output data. During system-level DUT testing, all communications between the system ATE and the chip are via a single interface, such as a conventional, serial JTAG port.

Abstract: An iterative PCCC encoder includes a first delay line operative to receive at least one input data sample and to generate a plurality of delayed samples as a function of the input data sample. The encoder further includes a second delay line including a plurality of delay elements connected in a series configuration. An input of a first one of the delay elements is adapted to receive a sum of first and second signals, the first signal generated as a sum of the input data sample and at least one of the delayed samples, and the second signal generated as an output of a single one of the delay elements. A third delay line in the encoder is operative to generate an output data sample as a function of the sum of the first and second signals and a delayed version of the sum of the first and second signals.

Abstract: Methods and structure are disclosed for improved processing of fast path I/O requests in a storage controller utilizing version information embedded in the fast path I/O requests. The version information allows the storage controller to determine if the mapping information utilized by the host system in generating a fast path I/O request specifies the mapping information utilized by the storage controller. The controller comprises a fast path I/O request processing circuit tightly coupled with host system drivers for fast processing of requests directed to storage devices of a logical volume. The controller also comprises a logical volume I/O processing software stack for processing I/O requests from a host system directed to a logical volume. If the mapping information utilized by the host does not match the mapping information utilized by the storage controller, fast path I/O requests are transferred to the I/O request processing stack for subsequent processing.