Abstract: A transceiver apparatus includes a process, a first type of transceiver circuit for data transmission, a second type of transceiver circuit for data transmission, and a communications interface for communicating between the first type of transceiver circuit and an external device. The first type of transceiver circuit is co-located with a physical layer associated with the first type of transceiver circuit. In some embodiments, the first type of transceiver circuit can be, for example, a USB 2.0 transceiver circuit, and the second type of transceiver circuit can be a USB 3.0 transceiver circuit. The aforementioned external device can be an external USB device.

Abstract: An apparatus including an adder, a delay line, and a first detector. The adder may be configured to generate an input signal in response to a received signal and a feedback signal. The feedback signal may include a contribution from each of a plurality of delayed versions of the input signal. The contribution from each of the plurality of delayed versions of the input signal may be determined by a respective weight value. The delay line may be configured to generate the plurality of delayed versions of the input signal. The first detector may be configured to recover a data sample from the input signal in response to a clock signal.

Abstract: A power measurement cell, or group of power measurement cells, for the calculation of the power consumption of one or more electrical signals, as well as monitoring electrical signals in an integrated circuit, are disclosed. Further, super cells for the automation of specialized functions associated with the calculation of power consumption of one or more electrical signals are also disclosed. Methods associated with the use of the one or more power measurement cells and for the use of super cells for the calculation of the power consumption of one or more electrical signals are also described.

Abstract: An apparatus for determining the presence of a tone in an input signal includes memory circuitry and data processing circuitry coupled to the memory circuitry. The data processing circuitry is operative to receive multiple samples of the input signal, and to determine a first value at least in part by multiplying each of the samples by respective ones of a first set of values for an impulse response and summing the results. The data processing system is also operative to determine a second value at least in part by multiplying each of a portion of the samples by respective ones of a second set of values for the impulse response and summing the results. The data processing system is operative to determine the power of the tone in the multiple samples of the input signal at least in part by utilizing the first value and the second value.

Abstract: A system and method for storing variable width stack elements in a single memory stack is disclosed. In one example embodiment a first variable width stack element is split into one or more sub-elements. The width of the sub-elements may be less than or equal to a width of the single memory stack. A first memory pointer is created for providing an address of a first read pointer in the single memory stack. The first read pointer may provide an address corresponding to a first sub-element of the first variable width stack element. The first sub-element is written in a first available location in the single memory stack. A write pointer of the single memory stack is incremented when the first sub-element is written to the first available location on the single memory stack. The steps of writing and incrementing are repeated for a next sub-element until all of the sub-elements are stored in the single memory stack.

Abstract: In a communication receiver, timing recovery circuitry includes a loop filter associated with a timing recovery loop of a first communication device. The first communication device is in communication with a second communication device prior to a temporary power down/power up sequence in the first communication device. The loop filter is configured to: (i) temporarily disable at least a portion of the timing recovery loop after the temporary power down/power up sequence in the first communication device; and (ii) initiate a progression through a set of potential sampling phases to determine a given sampling phase at which the first communication device can recommence communication with the second communication device.

Abstract: A lighting apparatus is shown and described. In one aspect, the lighting apparatus includes a lighting component and a mounting structure. The lighting component can include a light source, a plate, and a frame. The light source can include one or more lighting elements, such as light emitting diodes. The lighting component can be releasably secured to the mounting structure.

Abstract: Devices and systems for tool-less assembly of cable chains that are capable of being retractably stored. The device comprises a first contact element, a second contact element, and a lengthwise member. The first contact element is adapted for movable contact with a receiving member of a first cable chain segment. The second contact element is adapted for movable contact with a receiving member of a second cable chain segment. The lengthwise member is fixedly attached to the contact elements. When an angle between the first and the second cable chain segments is a first value, the lengthwise member experiences elastic deformation, generating a spring force at each contact element sufficient to pull the receiving member of the first cable chain segment rotatably towards the receiving member of the second cable chain segment, thereby reducing the angle between the first and the second cable chain segments to a second value.

Abstract: A flash-memory system is organized into a plurality of blocks and a plurality of pages in each block, each page having 2N data locations and K spare locations. At least one page in the memory has 2M user data sectors and each sector has 2N-M+L locations therein. Because L is at least 1 but less than 2N-M, user data is stored in the spare memory locations. By storing user data in spare locations that were previously off-limits to user data, enterprise-sized sectors can be efficiently stored in flash memories with little wasted memory, thereby making flash-memory systems compatible with existing hard-drive storage systems in enterprise system applications.

Abstract: Passivation integration schemes and pad structures to reduce the stress gradients and/or improve the contact surface existing between the Al in the pad and the gold wire bond. One of the pad structures provides a plurality of recessed pad areas which are formed in a single aluminum pad. An oxide mesa can be provided under the aluminum pad. Another pad structure provides a single recessed pad area which is formed in a single aluminum pad, and the aluminum pad is disposed above a copper pad and a plurality of trench/via pads. Still another pad structure provides a single recessed pad area which is formed in a single aluminum pad, and the aluminum pad is disposed above a portion of a copper pad, such that the aluminum pad and the copper pad are staggered relative to each other.

Abstract: A layered decoder that uses a non-standard schedule, where a non-standard schedule is a schedule where the frequency of one or more layers in the schedule is greater than one. When the layered decoder converges on a near codeword using an initial schedule, the layered decoder identifies the layer Lmaxb of the near codeword, which layer contains the greatest number of unsatisfied check nodes, and selects a subsequent non-standard schedule from a schedule set. The non-standard schedules in the schedule set are sorted by key layer, where the key layer is a layer that appears in the non-standard schedule with the greatest frequency. The layer decoder selects a non-standard schedule from the schedule set where the key layer of selected non-standard schedule is equal to the identified Lmaxb value.

Abstract: A data processing system comprises data processing circuitry, a cache memory, and memory access circuitry. The memory access circuitry is operative to assign a memory address region to be allocated in the cache memory with a predefined initialization value. Subsequently, a portion of the cache memory is allocated to the assigned memory address region only after the data processing circuitry first attempts to perform a memory access on a memory address within the assigned memory address region. The allocated portion of the cache memory is then initialized with the predefined initialization value.

Abstract: A memory device includes a memory array comprising a plurality of memory cells arranged in rows and columns, and sensing circuitry coupled to the memory array. The sensing circuitry comprises a plurality of output sense amplifiers configured to sense stored data associated with respective columns of the memory array, and sense amplifier control circuitry configured to generate a sense amplifier control signal for application to control inputs of respective ones of the output sense amplifiers. The sense amplifier control circuitry comprises reaction time tracking circuitry including at least one dummy sense amplifier configured to track reaction time of one or more of the output sense amplifiers, with the sense amplifier control signal being generated at least in part responsive to an output signal of the dummy sense amplifier.

Abstract: A protocol bridge includes a cache for caching data from a plurality of data storage devices, and for servicing data requests from a plurality of initiators. Data is cached for every data access operation such that the most frequently accessed data remains replicated in the cache.

Abstract: A system and method for improving message passing between a computer and peripheral devices is disclosed. The system and method for improving message passing between a computer and peripheral devices incorporate data checking on the command/message data and each scatter gather list element. The method in accordance with the present disclosure enables a peripheral device to check the integrity of the message and ownership of the scatter gather list element before the data is processed.

Abstract: An apparatus for handling anomalies in a hardware system including a master device and at least one slave device coupled with the master device through an interconnect device is provided. The apparatus includes at least one controller operative to receive status information relating to the slave device. The status information is indicative of whether an anomaly is present in the slave device and/or the interconnect device. The controller is operative to generate output response information as a function of the status information relating to the slave device for detecting and/or responding to hardware system anomalies in a manner which reduces a need for resetting the hardware system to return to normal operation.

Abstract: A light control system including a light source and a light management unit (LMU) operative to receive a light output control signal and to control a light output emitted from the light source, wherein the LMU controls the light output from the light source based on the light output control signal.

Abstract: A multiport latch-based memory device includes a latch array, a plurality of first multiplexers, and a second multiplexer. The latch array is responsive to output data from an input data register in a functional mode associated with the latch-based memory device. The plurality of first multiplexers is responsive to output data from the latch array in the functional mode. The plurality of first multiplexers is responsive to output data from the input data register in a test mode associated with the latch-based memory device. The second multiplexer selectively provides output data from the plurality of first multiplexers to the input data register in the test mode, thereby providing a data path bypassing the latch array in the test mode. Embodiments of a corresponding method and computer-readable medium are also provided.

Abstract: A method for generating and communicating file system hints. The method may include receiving an I/O request from a file system layer and checking the I/O request for file system contextual information. The method may also include accessing the file system layer to determine attributes of the file system contextual information and receiving the attributes of the file system contextual information from the file system layer. The method may further include analyzing attributes of the file system contextual information and generating a hint based upon analyzing the attributes of the file system contextual information. The method may include a mechanism to provide weight-age of data passed from the application. The hint may be associated with the I/O request, and the hint may comprise hotness information to increase efficiency of data accessibility at a lower level storage tier. The method may include sending the hint to the lower level storage tier.