Abstract: Described embodiments provide for scheduling packets for transmission by a network processor. A traffic manager generates a scheduling hierarchy having a root scheduler and N scheduler levels. The network processor generates tasks corresponding to received packets. A finite state machine (FSM) enqueues the received task in the associated queue. The queue has a corresponding scheduler level M, with a corresponding parent scheduler at each of M?1 levels in the scheduling hierarchy, where M is a positive integer less than or equal to N. Nodes at each of the N scheduling levels send messages only with one node at a relative next higher level and with one or more nodes at a relative next lower level. Each node in the scheduling hierarchy updates corresponding statistics and control indicators based on messages received from the node at the next higher level and the one or more nodes at the next lower level.

Abstract: In described embodiments, a Serializer-Deserializer (SerDes) receiver includes a pattern detector that allows for detection of insufficiently randomized pattern periods and low activity periods. A freeze of equalization adaptation during these periods might occur by embedding disqualifying patterns into adaptation data. Some embodiments also allow for detection of long intervals of freeze, and so delay a freeze de-assertion in order for a clock and data recovery (CDR) circuit of the receiver to regain lock to the serial data. Embedding freeze information in the receive data allows for precise synchronization of receive data and freeze.

Abstract: Systems and methods of voltage based switching of a power supply system current are disclosed. In one embodiment, a power supply system includes a power bus to supply electrical power to a system load. A power supply is coupled to the power bus. The power supply provides current to the power bus and generates a voltage ?. In addition, the system includes an additional power supply coupled to the power bus. The additional power supply generates a voltage ? that is lower than the voltage ?. An oring module restricts the additional power supply from providing current to the power bus, until a power bus voltage ? is greater than a threshold voltage.

Abstract: An electronic device package includes first and second electrodes of a package substrate. The first electrode has fingers formed from a first metal level and is configured to operate at a first DC potential. The second electrode has fingers formed from the first metal level interdigitated with the fingers of the first electrode. A via conductively connects the second electrode to a second metal level. The second metal level is configured to operate at a second DC potential. The first and second DC potentials are thereby capacitively coupled through the interdigitated electrodes.

Abstract: In order to compensate for phase offset between different sets of circuitry having different synchronous clock domains, transmit (TX) circuitry of one domain is configured to transmit a pattern signal (e.g., a pseudo random bit sequence) to receive (RX) circuitry of the other domain. The RX circuitry cycles through a number of different phase-shifted RX clock signals to determine which selected clock signals result in valid RX pattern signals. The RX circuitry is then able to select one of the phase-shifted clock signals for use in normal processing of an RX data signal received from the TX circuitry.

Abstract: A low-density parity check min-sum decoder including a variable node processing unit having N+1 inputs. A first bank of N+1 two-input adders each have an associated output, and at least one of the N+1 inputs go to more than two of the adders of the first bank. A second bank of N two-input adders has no adders in common with the first bank. At least one of the adders of the first bank provides its associated output to more than one adder of the second bank. The banks of adders are disposed in series. A sign module outputs a sign value produced from one of the inputs and an output from one of the adders of the second bank. N+1 outputs are provided, where one of the outputs is the sign value.

Abstract: Systems and methods are described for the control of lighting systems at individual light-fixture, local, regional, and larger-geographical-area levels that also distribute electrical power to consumers. One implementation comprises a hierarchical lighting-control system including an automated network-control center that may control up to many millions of individual lighting fixtures and lighting elements, regional routers interconnected to the network-control center or network-control centers by public communications networks, each of which controls hundreds to thousands of individual light fixtures, and light-management units, interconnected to regional routers by radio-frequency communications and/or power-line communications, each of which controls components within a lighting fixture, including lighting elements, drivers, sensors, and other devices. Systems and methods of using synthetic events for calibration and control of lighting systems are also described.

Abstract: An adaptive voltage scaling system includes first and second devices. Each of the first and second devices includes at least one master serial interface port and at least one slave serial interface port. The first device is operatively coupled to a voltage regulator, and the slave serial interface port associated with the second device is operatively coupled to the master serial interface port associated with the first device. The first device controls the voltage regulator based on information obtained from the first and second devices using the master serial interface port associated with the first device and the slave serial interface port associated with the second device. The first and second devices receive voltage from the voltage regulator. A corresponding method and computer-readable medium are also disclosed.

Abstract: A base station of a wireless system comprises a local clock source and timing circuitry coupled to the local clock source. The timing circuitry is configured to adjust at least one parameter of the local clock source based at least in part on timing information extracted from designated portions of each of one or more frames of a synchronous transport signal received in the base station. The base station may further comprise a physical layer device, such as a mapper, configured to extract the timing information from the designated portions of each of the one or more frames of the synchronous transport signal. The designated portions of the one or more frames of the synchronous transport signal from which the timing information is extracted may comprise designated overhead bytes of the one or more frames, such as, for example, transport overhead (TOH) bytes.

Abstract: Irrigation control systems and method of operating an irrigation system are described for irrigation systems including one or more orifices, e.g., sprinkler heads, arranged in one or more irrigation lines. The control system can include one or more sensors such as moisture meters and flow meters that measure water output associate with the irrigation system. The irrigation control system can be linked to one or more networks for access, e.g., through the Internet. The control systems and methods can utilize moisture calibration to avoid or reduce a need for continuous use of moisture sensors.

Abstract: Methods and structure for rapid offloading of cached data in a volatile cache memory of a storage controller to a nonvolatile memory. Features and aspects hereof provide an enhanced storage controller having a volatile cache memory and multiple communication channels each coupled with a corresponding nonvolatile memory device. Responsive to detecting an impending loss of power, control logic of the controller copies data from the volatile cache memory to the multiple nonvolatile memories using the multiple communication channels operating substantially in parallel. Using multiple parallel channels and nonvolatile memory substantially temporally overlapping their operations assures that the cached data can be saved to nonvolatile memory before the controller is inoperable due to power loss. A simple “file system” and error detection and correction codes on the nonvolatile memory help assure that the saved data is valid for return to the volatile memory when power is restored to the controller.

Abstract: A method of designing an integrated circuit, integrated circuits using different drive strengths and a signal integrity monitor are provide herein. In one embodiment, the signal integrity monitor includes: (1) a signal interface configured to receive a signal from a parallel data bus for transmission over a plurality of signal paths and (2) a victim signal identifier configured to dynamically determine a potential victim signal path of the plurality of signal paths.

Abstract: A system, method, and computer program product are provided for sending failure information from a solid state drive (SSD) to a host device. In operation, an error is detected during an operation associated with a solid state drive. Additionally, a command is received for failure information from a host device. Further, the failure information is sent from the solid state drive to the host device, the failure information including failure information associated with the solid state drive.

Abstract: A method of designing a model of an integrated circuit block, an electronic design automation tool and a non-transitory computer-readable medium are disclosed herein. In one embodiment, the method includes: (1) generating an input and output timing budget for the block based on design constraints of the block and a netlist of the block, (2) updating the input and output timing budget with clock customization data based on designer knowledge of the integrated circuit and (3) providing the model for the block based on the update of the input and output timing budget, wherein the model represents clock information of the block separately from data path information of the block.

Abstract: Disclosed is a method of reliably operating a RAID storage system. A first block of data is striped across a plurality of drives following a CRUSH algorithm. The first block of data is again striped across a second plurality of drives to a D?+P? stripe and placed on free drive space following the CRUSH algorithm. The data is written in an asynchronous fashion and possibly at a time when system utilization is low.

Abstract: Various embodiments of the present invention provide systems and methods for data processing that includes selectively reporting results out of order or in order.

Abstract: A SAS expander configured to operate as a SAS expander hub receives IO requests from connected SAS expanders and relays the IO requests to SAS expanders connected to data storage devices capable of servicing such IO requests.

Abstract: A lighting apparatus is shown and described. In one aspect, the lighting apparatus includes a light source, a plate, and frame. The light source can include one or more lighting elements that are in thermal communication with the light source. The plate can have a dissipative portion extending outward from a point of thermal communication between the plate and the light source. The frame can at least partially enclose the light source and may also be in thermal communication therewith.

Abstract: A transceiver comprises a transmitter and a receiver. At least one of the transmitter and the receiver comprises an adaptive filer. One or more coefficients of the adaptive filter are determined based at least in part on an output of a real time clock. The adaptive filter may comprise a coefficient update engine and a memory for storing a plurality of sets of adaptive filter coefficients in association with respective time indicators derived from the output of the real time clock, with the coefficient update engine being configured to determine a particular one of the sets of filter coefficients for use by the adaptive filter based at least in part on at least a subset of the time indicators. The time indicators may comprise respective time stamps generated based on the output of the real time clock at respective times at which the corresponding sets of coefficients are determined.

Abstract: A Solid-State Disk (SSD) controller enables dynamic higher-level redundancy mode management with independent silicon elements to provide graceful degradation as non-volatile (e.g. flash) memory elements fail during operation of an SSD implemented by the controller. Higher-level error correction provides correction of lower-level uncorrectable errors. If a failure of one of the non-volatile memory elements is detected, then the higher-level error correction is dynamically transitioned from operating in a current mode to operating in a new mode. The transition includes one or more of reducing free space available on the SSD, rearranging data storage of the SSD, recovering/storing failed user data (if possible), and determining/storing revised higher-level error correction information. Operation then continues in the new mode. If another failure of the non-volatile memory elements is detected, then another transition is made to another new mode.