Patents Assigned to LTD.
  • Patent number: 12381148
    Abstract: A semiconductor structure includes an isolation structure formed on a substrate, a gate-all-around transistor structure formed on the isolation structure, a via electrically coupled to a gate terminal of the gate-all-around transistor structure, and a buried conductive pad formed within the isolation structure and electrically coupled to the via. The buried conductive pad can extend through the isolation structure in two dimensions, such as in both a vertical dimension and a horizontal dimension. The semiconductor structure can provide advantages in terms of routing flexibility, among other possible advantages.
    Type: Grant
    Filed: June 3, 2024
    Date of Patent: August 5, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Guo-Huei Wu, Pochun Wang, Chih-Liang Chen, Li-Chun Tien
  • Patent number: 12380863
    Abstract: A display device includes a display panel including a plurality of pixels and a plurality of data lines connected to the pixels, and a data driver which provide a plurality of data voltages to the data lines. The data driver includes a plurality of channels, where each of the channels outputs an nth data voltage in an nth horizontal period, and outputs an (n+1)th data voltage in an (n+1)th horizontal period, where n is a natural number, a common line, a plurality of data switches, which selectively connect the channels to the data lines, respectively, a plurality of common switches, each of which selectively connects a corresponding one of the channels to the common line, and a voltage sensor which senses a common voltage of the common line.
    Type: Grant
    Filed: March 19, 2024
    Date of Patent: August 5, 2025
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Taegon Im, Youngmin Bae, Jinyoung Jeon
  • Patent number: 12380914
    Abstract: Disclosed are a display apparatus, a voice acquiring apparatus and a voice recognition method thereof, the display apparatus including: a display unit which displays an image; a communication unit which communicates with a plurality of external apparatuses; and a controller which includes a voice recognition engine to recognize a user's voice, receives a voice signal from a voice acquiring unit, and controls the communication unit to receive candidate instruction words from at least one of the plurality of external apparatuses to recognize the received voice signal.
    Type: Grant
    Filed: December 20, 2022
    Date of Patent: August 5, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-hyuk Jang, Chan-hee Choi, Hee-seob Ryu, Kyung-mi Park, Seung-kwon Park, Jae-hyun Bae
  • Patent number: 12380937
    Abstract: A FRAM memory device can include a plurality of FRAM memory cells, each FRAM memory cell including one transistor and one capacitor electrically coupled to the at least one transistor. The capacitor can be configured to store a bit of data. The memory device can also include a local bit-line configured to carry data to be read from or written to the plurality of memory cells. The memory device can further include a global bit-line configured to communicate with the local bit-line to carry the data to be read from or written to the plurality of memory cells. The memory device can additionally include a local sense amplifier configured to amplify a signal in the local bit-line and transfer the amplified signal to the global bit-line based on a reference signal. The local sense amplifier can be configured to generate the amplified signal based on comparison to the reference signal.
    Type: Grant
    Filed: July 7, 2023
    Date of Patent: August 5, 2025
    Assignee: WUXI SMART MEMORIES TECHNOLOGIES CO., LTD.
    Inventor: Feng Pan
  • Patent number: 12382667
    Abstract: A thin film transistor and a display device comprising the same are provided. The thin film transistor comprises a first gate electrode and a second gate electrode, which are spaced apart from each other to overlap each other, and an active layer disposed between the first gate electrode and the second gate electrode, including a first active layer and a second active layer, wherein the active layer includes a channel portion, a first connection portion that is in contact with one side of the channel portion, and a second connection portion that is in contact with the other side of the channel portion. The channel portion includes a first channel portion and a second channel portion, which are disposed in parallel.
    Type: Grant
    Filed: October 31, 2022
    Date of Patent: August 5, 2025
    Assignee: LG Display Co., Ltd.
    Inventors: Dohyung Lee, HongRak Choi, ChanYong Jeong
  • Patent number: 12382671
    Abstract: The present disclosure provides a semiconductor device and a method for fabricating a semiconductor device. The semiconductor device includes a substrate, a metal gate layer over the substrate, a channel between a source region and a drain region in the substrate, and a ferroelectric layer, at least a portion of the ferroelectric layer is between the metal gate layer and the substrate, wherein the ferroelectric layer includes hafnium oxide-based material, the hafnium oxide-based material includes a first portion of hafnium oxide with orthorhombic phase, a second portion of hafnium oxide with monoclinic phase, and a third portion of the hafnium oxide with tetragonal phase, wherein a first volume of the first portion is greater than a second volume of the second portion, and the second volume of the second portion is greater than a third volume the third portion.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: August 5, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun-Yen Peng, Chih-Yu Chang, Bo-Feng Young, Te-Yang Lai, Sai-Hooi Yeong, Chi On Chui
  • Patent number: 12382675
    Abstract: The semiconductor device comprises a high-voltage device region, a low-voltage device region, and an isolation region. It further comprises a drift region, a second conductivity type well region, an isolation well region, an isolation structure, a power device source region, and a power device drain region. The drift region is disposed in the high-voltage device region. The second conductivity type well region is disposed in the isolation region and extends to the low-voltage device region. The isolation well region is disposed in the drift region and separates the drift region into a high-voltage drift region and a power device drift region. The isolation structure is disposed in the isolation well region. The power device source region is disposed in the isolation region and located in the second conductivity type well region, and the power device drain region is disposed in the power device drift region.
    Type: Grant
    Filed: April 6, 2023
    Date of Patent: August 5, 2025
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: Teng Liu, Nailong He, Lihui Gu, Sen Zhang, Wentong Zhang
  • Patent number: 12382693
    Abstract: Some implementations described herein provide a nanostructure transistor including inner spacers between a gate structure and a source/drain region. The inner spacers, formed in cavities at end regions of sacrificial nanosheets during fabrication of the nanostructure transistor, include concave-regions that face the source/drain region. Formation techniques include forming the sacrificial nanosheets and inner spacers to include certain geometric and/or dimensional properties, such that a likelihood of defects and/or voids within the inner spacers and/or the gate structure are reduced.
    Type: Grant
    Filed: April 28, 2022
    Date of Patent: August 5, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Wei Chang, Shahaji B. More, Chi-Yu Chou, Chun Chieh Wang, Yueh-Ching Pai
  • Patent number: 12382703
    Abstract: A semiconductor device includes a base portion on a semiconductor substrate, a channel layer vertically above the base portion and extending parallel to a top surface of the semiconductor substrate, a gate portion between the channel layer and the base portion, a source/drain feature connected to the channel layer, an inner spacer between the source/drain feature and the gate portion, and an air gap between the source/drain feature and the semiconductor substrate. Moreover, a bottom surface of the source/drain feature is exposed in the air gap.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: August 5, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: I-Hsieh Wong, Alex Lee, Wei-Han Fan, Tzu-Hua Chiu, Wei-Yang Lee, Chia-Pin Lin
  • Patent number: 12382704
    Abstract: A semiconductor device includes: a first source/drain region; a second source/drain region; a channel between the first source/drain region and the second source/drain region; an interfacial insulating layer on the channel; a ferroelectric layer on the interfacial insulating layer; and a gate electrode on the ferroelectric layer, wherein, when a numerical value of dielectric constant of the interfacial insulating layer is K and a numerical value of remnant polarization of the ferroelectric layer is Pr, a material of the interfacial insulating layer and a material of the ferroelectric layer are selected so that K/Pr is 1 or more.
    Type: Grant
    Filed: September 15, 2022
    Date of Patent: August 5, 2025
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seunggeol Nam, Hyunjae Lee, Dukhyun Choe, Jinseong Heo
  • Patent number: 12382714
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a fin-based structure formed on a substrate. The semiconductor device includes a plurality of first nanosheets, vertically spaced apart from one another, that are formed on the substrate. The semiconductor device includes a first source/drain (S/D) region electrically coupled to a first end of the fin-based structure. The semiconductor device includes a second S/D region electrically coupled to both of a second end of the fin-based structure and a first end of the plurality of first nanosheets. The semiconductor device includes a third S/D region electrically coupled to a second end of the plurality of first nanosheets. The fin-based structure has a first crystal lattice direction and the plurality of first nanosheets have a second crystal lattice direction, which is different from the first crystal lattice direction.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: August 5, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Sheng Chang, Chia-En Huang, Yih Wang
  • Patent number: 12382718
    Abstract: A semiconductor device may include an active pattern on a substrate, a lower channel pattern on the active pattern and including first and second lower semiconductor patterns, an upper channel pattern on the lower channel pattern and including first and second upper semiconductor patterns, a pair of lower source/drain patterns on opposite sides of the lower channel pattern and a pair of upper source/drain patterns on opposite sides of the upper channel pattern, and a gate electrode surrounding the lower and upper channel patterns. The gate electrode may include a first upper portion between the first and second upper semiconductor patterns, and a first lower portion between the first and second lower semiconductor patterns. Each semiconductor pattern may include a first recess part having a first recess region on a top surface thereof, and a first protrusion part protruding from a bottom surface of the first recess part.
    Type: Grant
    Filed: September 29, 2022
    Date of Patent: August 5, 2025
    Assignees: Samsung Electronics Co., Ltd., KOREA UNIVERSITY Research and Business Foundation
    Inventors: Hyun-Yong Yu, Seung Geun Jung
  • Patent number: 12382723
    Abstract: A semiconductor device is described, which includes a first transistor, a second transistor, and a capacitor. The second transistor and the capacitor are provided over the first transistor so as to overlap with a gate of the first transistor. A semiconductor layer of the second transistor and a dielectric layer of the capacitor are directly connected to the gate of the first transistor. The second transistor is a vertical transistor, where its channel direction is perpendicular to an upper surface of a semiconductor layer of the first transistor.
    Type: Grant
    Filed: August 17, 2023
    Date of Patent: August 5, 2025
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kensuke Yoshizumi
  • Patent number: 12382746
    Abstract: The present application relates a solar cell, a photovoltaic device and a photovoltaic system. The solar cell includes a substrate, a first passivation layer, and a second passivation layer. The substrate includes a first surface and a second surface opposite to each other along a thickness direction of the substrate. The first passivation layer is disposed on the first surface of the substrate. The second passivation layer is disposed on a side of the first passivation layer away from the substrate. A material of the first passivation layer is the same as that of the second passivation layer. An atomic packing density of the first passivation layer is higher than that of the second passivation layer. An average thickness of the first passivation layer is smaller than that of the second passivation layer.
    Type: Grant
    Filed: October 24, 2023
    Date of Patent: August 5, 2025
    Assignee: TRINA SOLAR CO., LTD.
    Inventors: Chengfa Liu, Shuai Zhang, Hong Chen, Yugang Lu, Wanli Li, Yang Zou
  • Patent number: 12382481
    Abstract: A communication method and devoice, the method including receiving, by a terminal device, indication information sent by a radio access network device, where the indication information is generated by the radio access network device based on configuration information that is used by the terminal device to transmit service data on a sidelink, and where the configuration information include any one or more of a technology type, an air interface, a radio access technology, and a mode that are used by the terminal device to transmit the service data on the sidelink, wherein the sidelink is a wireless communication link between the terminal device and another terminal device, and transmitting, by the terminal device, the service data on the sidelink based on the indication information.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: August 5, 2025
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Wenjie Peng, Jun Wang, Mingzeng Dai
  • Patent number: 12382502
    Abstract: Embodiments of this application provide a random access response method and an apparatus. The method includes: RARs associated with one RO are transmitted based on groups, so that a transport block size of RAR data transmitted each time is reduced, and N bits in DCI format 1_0 of CRC are scrambled by using a RA-RNTI to indicate scheduling information of N RAR groups in a PDSCH. Alternatively, DCI format 1_0 of CRC is scrambled by using identifiers of RAR groups, to correspondingly schedule the RAR groups in the PDSCH. According to this application, a problem of a large transport block caused by a large quantity of RARs being transmitted in a PDSCH can be avoided, so that a modulation order or a bit rate is reduced, and demodulation performance of a terminal device is improved.
    Type: Grant
    Filed: August 26, 2022
    Date of Patent: August 5, 2025
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Hailong Hou, Yongqiang Fei, Chaojun Li, Juan Zheng
  • Patent number: 12382514
    Abstract: The present disclosure relates to channel conflict processing methods and apparatus. In one example method, when a terminal device establishes a connection relationship with a source cell, and sends a connection request to or establishes a connection relationship with a target cell, the terminal device detects whether an uplink channel conflict occurs on an uplink channel of the source cell and an uplink channel of the target cell, where the source cell and the target cell are infra-frequency or intra-band contiguous inter-frequency. If the terminal device determines that an uplink channel conflict occurs, the terminal device sends a signal on an uplink channel with a higher priority between the uplink channel of the source cell and the uplink channel of the target cell.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: August 5, 2025
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Yan Chen, Le Jin, Bingguang Peng, Xi Zhang
  • Patent number: 12382515
    Abstract: Disclosed in the present application are a method and apparatus for reporting a random access procedure. The method includes: receiving a first message sent by a network device, the first message being used to indicate the terminal device to report a random access parameter list to the network device, and the random access parameter list including a two-step random access parameter list and/or a four-step random access parameter list; and reporting the random access parameter list to the network device according to the first message.
    Type: Grant
    Filed: October 14, 2022
    Date of Patent: August 5, 2025
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventors: Xue Lin, Cong Shi
  • Patent number: 12382517
    Abstract: A power saving method, a terminal, an access network device, and a readable storage medium, pertains to the field of communications, wherein the method includes: performing, by a terminal, physical downlink control channel (PDCCH) monitoring on a duration timer within a first number N1 of DRX cycles in response to detecting a power saving signal; skipping, by the terminal, the PDCCH monitoring on a duration timer within a second number N2 of DRX cycles in response to detecting no wake up signaling. The first number N1 and the second number N2 are identical or different.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: August 5, 2025
    Assignee: BEIJING XIAOMI MOBILE SOFTWARE CO., LTD.
    Inventor: Yanhua Li
  • Patent number: 12382528
    Abstract: The present disclosure relates to radio resource control (RRC) reestablishment methods and apparatuses. In one example method, a terminal device selects a target cell, where the target cell supports an expected network slice. The terminal device sends an RRC reestablishment request message by using the target cell. The expected network slice may include a network slice that the terminal device expects to access, or a network slice corresponding to a PDU session established by the terminal device by using a last serving access network device of the terminal device. The terminal device may select the target cell within a preset time period. For example, the terminal device starts a first timer when the terminal device starts selecting the target cell, and selects the target cell during running of the first timer. The first timer may be specific to one or more network slices or all network slices.
    Type: Grant
    Filed: October 14, 2022
    Date of Patent: August 5, 2025
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Chunhua You, Qinghai Zeng, Haiyan Luo, Chong Lou