Abstract: Disclosed is an amplifying circuit and method. In one embodiment, an amplifying circuit, includes: a common-gate (CG) amplifier, wherein the CG amplifier comprises a first transistor, wherein source terminal and body terminal of the first transistor is coupled together through a first resistor.

Abstract: A switching circuit includes a first switch; a second switch connected in series with the first switch; a first isolated driver connected to a gate terminal of the first switch; a second isolated driver connected to a gate terminal of the second switch; and a transformer including a primary winding connected to an auxiliary power supply, a first secondary winding to supply a first voltage to the first isolated driver, and a second secondary winding to supply a second voltage to the second isolated driver.

Abstract: An electronic device according to various embodiments comprises: a universal serial bus (USB) interface for configuration channel (CC) communication with an external device; a power management IC (PMIC) for power control of the electronic device; and a processor operatively connected to the USB interface and the PMIC.

Abstract: A method for responding to a query, the method may include (a) receiving, by a storage system compute element, a query that comprises one or more conditions related to a content of at least one data unit (DU); (b) searching, based on the one or more conditions and on a condition fulfillment information (CFI), for one or more irrelevant groups of DUs to be skipped during the responding to the query; wherein the one or more irrelevant groups of DUs belong to multiple stored groups of DUs that are stored in the storage system; wherein an irrelevant group of DU does not comprise, according to the CFI, any DU that fulfills the one or more conditions; and (c) generating a response to the query based on an outcome of the searching.

Abstract: A method of forming an integrated circuit includes forming at least a first or a second set of devices in a substrate, forming an interconnect structure over the first or second set of devices, and depositing a set of conductive structures on the interconnect structure. The first and second set of devices are configured to operate on a first supply voltage. Forming the interconnect structure includes depositing a set of insulating layers over the first or second set of devices, etching the set of insulating layers thereby forming a set of trenches, depositing a conductive material within the set of trenches, thereby forming a set of metal layers, and forming a portion of a header circuit between a first and a second metal layer. The header circuit is configured to provide the first supply voltage to the first set of devices.

Abstract: A document creation method, and a device and a storage medium are provided. The method comprises: in an editing interface of the current document, calling an operation panel according to a trigger event, and displaying the operation panel; displaying a creation control of a reference object in the operation panel; and in response to an operation of a user for the creation control, creating a new reference object, and establishing a reference relationship between the current document and the reference object.

Abstract: The present disclosure discloses an adaptive high-precision compression method and system based on a convolutional neural network model, and belongs to the fields of artificial intelligence, computer vision, and image processing. According to the method of the present disclosure, coarse-grained pruning is performed on a neural network model by using a differential evolution algorithm first, and the coarse-grained space is quickly searched through an entropy importance criterion and an objective function with good guidance to obtain a near-optimal neural network structure. Then fine-grained search space is built on the basis of an optimal individual obtained from the coarse-grained search, and fine-grained pruning is performed on the neural network model by a differential evolution algorithm to obtain a network model with an optimal structure. Finally, the performance of the optimal model is restored by using a multi-teacher multi-step knowledge distillation network to reach the precision of an original model.

Abstract: Some embodiments of the present disclosure provide an infrared-transmitting housing for preventing light interference and an infrared positioning handle. The infrared-transmitting housing for preventing light interference includes a first housing and a second housing disposed on an outer side of the first housing, wherein the first housing is an infrared-transmitting member and the second housing is a light-shielding member; the second housing is provided with a via corresponding to a position of an infrared lamp of an external device; and the first housing and the second housing are integrally formed by a two-shot injection molding.

Abstract: A backlight module of an illuminated keyboard includes: a circuit board including a first circuit, a second circuit, a gathering portion and a conduction portion, and the first circuit having a first line section; a light guiding plate disposed on the circuit board, including a first light guiding region and a second light guiding region, and the first light guiding region disposed on the first line section; a plurality of light-emitting elements disposed in parallel on the first line section; and an resistor unit including a first resistor and a second resistor, the first resistor disposed on the first circuit, and the second resistor disposed on the second circuit. A sum of a line impedance of the first circuit and an impedance of the first resistor is substantially equal to a sum of a line impedance of the second circuit and an impedance of the second resistor.

Abstract: A memory power control command may be received from a host and may include either a first power control command or a second power control command. The first power control command may correspond to the host not using a memory device, and the second power control command may correspond to the host using the memory device. It may be determined whether to activate a memory processor based on the memory power control command and on memory processor activation information. When the memory processor is activated based on the determining, an operation of the memory processor may be started based on the first power control command or ended based on the second power control command. When the memory processor is inactivated based on the determining, it may be determined whether to activate or inactivate the memory based on the memory power control command.

Abstract: This application provides a multi-screen data processing method, an electronic device, and readable storage medium, and belongs to the field of electronic device technologies. The electronic device includes: a control chip including a first display serial interface DSI and a second display serial interface DSI, where the first DSI and the second DSI are connected with input ports of a display chip respectively and are configured to provide a first data signal to the display chip; an output port of the display chip is connected with a first display of a plurality of displays, the control chip is configured to control the display chip to output the first data signal or a second data signal to the first display; and/or the control chip is configured to control the output port of the display chip to output first data or second data to a second display other than the first display.

Abstract: This application relates to the field of computer technologies, and discloses methods and apparatuses, for example, for rectifying a weak memory ordering problem. An example method includes: determining a read/write instruction set in to-be-repaired code; classifying instructions in the read/write instruction set to determine a target instruction; and inserting a memory barrier instruction between a previous read/write instruction of the target instruction and the target instruction. The read/write instruction set includes a read instruction and/or a write instruction in the to-be-repaired code, and an instruction in the read/write instruction set is used for memory access.

Abstract: A pixel circuit includes a capacitor, a light emitting control transistor, a driving transistor, and multiple light emitting transistors. The light emitting control transistor includes a gate electrode coupled to a light emitting control signal, a source electrode coupled to a supply voltage, and a drain electrode. The driving transistor includes a gate electrode coupled to the capacitor, a source electrode coupled to the drain electrode of the light emitting control transistor, and a drain electrode. Each light emitting transistor includes a gate electrode coupled to a respective light emitting signal, a source electrode coupled to the drain electrode of the driving transistor, and a drain electrode coupled to a respective light emitting element. Each light emitting signal turns on the respective light emitting transistor during a respective light emitting period within a frame period to cause the respective light emitting element to emit a light.

Abstract: Provided is a display device including a substrate, a circuit layer disposed on a first surface of the substrate, a light emitting element layer, and a circuit board disposed on a second surface of the substrate. The circuit layer includes pixel drivers, gate lines, a first power supply line and a second power supply line respectively transmitting a first power and a second power, and a gate driver including stages electrically connected to the gate lines, respectively. The second power supply line is electrically connected to the circuit board through power connection portions. The power connection portions are disposed between a number of the stages adjacent to a curved corner of the substrate among the stages of the gate driver.

Abstract: A memory device with shortened access time in data reading is provided. The memory device includes a first layer and a second layer positioned above the first layer, the first layer includes a reading circuit, and the second layer includes a first memory cell and a second memory cell. The reading circuit includes a Si transistor. The first memory cell and the second memory cell each include an OS transistor. The first memory cell is electrically connected to the reading circuit, and the second memory cell is electrically connected to the reading circuit. When a first current corresponding to first data retained in the first memory cell flows from the reading circuit to the first memory cell and a second current corresponding to second data retained in the second memory cell flows from the reading circuit to the second memory cell, the reading circuit compares the current amounts of the first current and the second current, and reads the first data.

Abstract: A memory device includes a plurality of memory cells; a word line, connected to one of the plurality of memory cells, that is configured to provide a first WL pulse having a rising edge and a falling edge that define a pulse width of the first WL pulse; a first tracking WL, formed adjacent to the memory cells, that is configured to provide, via being physically or operatively coupled to a bit line (BL) configured to write a logic state to the memory cell, a second WL pulse having a rising edge with a decreased slope; and a first tracking BL, configured to emulate the BL, that is coupled to the first tracking WL such that the pulse width of the first WL pulse is increased based on the decreased slope of the rising edge of the second WL pulse.

Abstract: A method of performing an in-memory computation includes storing a first subset of data in a first segment of a first memory array and a second subset of the data in a second segment of the first memory array, latching a first data bit from a first column of memory cells in the first segment of the first memory array, sequentially reading a plurality of second data bits from a second column of memory cells in the second segment of the first memory array, and performing a logic operation on each combination of the latched first data bit and each second data bit.

Abstract: An electronic device may include: a camera module comprising a wide angle camera configured to generate a wide image and a telephoto camera configured to generate teleimages corresponding to grid cells of the wide image; and one or more processors configured to: partition the teleimages into partial teleimages; determine partial wide images corresponding to the partial teleimages based on subcells of the grid cells and the wide image; perform feature matching between the partial teleimages and the partial wide images; determine a warping parameter of the teleimages based on a result of the feature matching; and generate a synthetic image corresponding to the wide image by warping the teleimages based on the warping parameter.

Abstract: Disclosed are a method and apparatus for training an image restoration model, an electronic device, and a computer-readable storage medium. The method for training an image restoration model includes: pre-processing training images to obtain a low-illumination image sample set (110); determining, based on low-illumination image samples in the low-illumination image sample set and the image restoration model, a weight coefficient of the image restoration model (120), wherein the image restoration model is a neural network model determined on a U-Net network and a deep residual network; and adjusting the image restoration model according to the weight coefficient, and further training the adjusted image restoration model using the low-illumination image samples until the image restoration model restores parameters of all the low-illumination image samples in the low-illumination image sample set into a preset range (130).

Abstract: A photo resist layer is used to protect a dielectric layer and conductive elements embedded in the dielectric layer when patterning an etch stop layer underlying the dielectric layer. The photo resist layer may further be used to etch another dielectric layer underlying the etch stop layer, where etching the next dielectric layer exposes a contact, such as a gate contact. The bottom layer can be used to protect the conductive elements embedded in the dielectric layer from a wet etchant used to etch the etch stop layer.