Abstract: This application discloses a display method and an electronic device, and relates to the field of terminal technologies. The method includes: sending, by the electronic device in response to a first operation, a profile download request to an operator network; and receiving a profile, where the profile includes profile metadata, and the profile metadata includes at least one field; and in response to a second operation, displaying a first screen on a display based on the profile metadata, where the first screen includes at least one of a first option indicating a network standard, a second option indicating a card type, a third option indicating account balance information of the profile, a fourth option indicating information about a remaining data volume of an account data plan, and a fifth option indicating a state of an account. This allows a user to learn profile capabilities before activating the profile.

Abstract: This application provides a security authentication method and apparatus applied to Wi-Fi, to help prevent a password from being shared among a plurality of devices, and implement management of a second device by a first device. In the method, an access point AP receives a first password input by the first device, where the first password is a password preset before delivery; and when checking the first password by the AP succeeds, the AP obtains a second password shared between the AP and the first device, and performs a 4-way handshake with the first device based on the second password. The second password is a shared key between the first device and the AP. Then, the AP can receive a first request from the first device, and send a third password to the first device in response to the first request.

Abstract: The present disclosure provides for methods, apparatuses, and non-transitory computer-readable storage media for load balancing traffic scenarios by a network device. In an embodiment, a method includes training a plurality of learning agents to load balance a respective plurality of traffic scenarios to obtain a plurality of control policies. The method further includes performing at least one clustering iteration. Each clustering iteration includes selecting a pair of control policies and merging the pair of control policies into a clustered control policy that replaces the pair of control policies. The method further includes determining to stop the performing of the at least one clustering iteration when a quantity of control policies remaining in the plurality of control policies meets a predetermined value. The method further includes deploying to each base station of a plurality of base stations a corresponding control policy from the plurality of control policies.

Abstract: A method performed by an integrated access backhaul (IAB) node in a wireless communication system is provided. The method comprises: receiving, from a base station, configuration information regarding an uplink (UL) grant, receiving, from the base station, configuration information regarding backhaul (BH) radio link control (RLC) channel via higher layer signaling, identifying, based on the configuration information regarding BH RLC channel, whether an extended logical channel identifier (eLCID) is used, in case that the eLCID is not used and a UL grant size is equal to or larger than a first size, not transmitting only a padding buffer status report (BSR) or not transmitting only padding or not transmitting only the padding BSR and the padding, and in case that the eLCID is used and the UL grant size is equal to or larger than a second size, not transmitting only the padding BSR or not transmitting only the padding or not transmitting only the padding BSR and the padding.

Abstract: A valve structural body that is easy to attach to a container is for a power storage device, and includes a casing in which a passage through which gas generated inside of the container is discharged to the outside of the container is formed, and a valve mechanism that is accommodated in the casing and allows the gas to pass through the passage to the outside of the container via the passage if the internal pressure of the container has risen due to the gas generated inside of the container. The casing includes a first plane, and a second plane that is parallel to the first plane.

Abstract: The insulating film assembly includes a first insulating film and a second insulating film. The first insulating film is provided with a first buffering via. The first insulating film and the second insulating film are opposite to each other. The second insulating film is provided with a second buffering via. An orthographic projection of the second buffering via on the first insulating film and the first buffering via do not have overlapping regions. The first insulating film is further provided with a first buffering groove, and the first buffering groove communicates with the first buffering via. The second insulating film is further provided with a second buffering groove, and the second buffering groove communicates with the second buffering via. An orthographic projection region of the second buffering groove on the first insulating film at least partially overlaps with the first buffering groove.

Abstract: The disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). According to embodiments of the present disclosure, an electronic device may include: a printed circuit board (PCB); an antenna; a radome; and a coupling structure, the antenna may be disposed to be positioned at a first height from a first surface of the PCB, the coupling structure may be physically connected with the radome, and the coupling structure may be disposed to have a second height lower than or equal to the first height, with respect to the first surface of the PCB.

Abstract: A dual-band antenna of the present disclosure includes: a dielectric substrate having a first surface and a second surface disposed opposite each other in a thickness direction of the dielectric substrate; a reference electrode disposed on the first surface; all of the radiating element, the first feed branch and the second feed branch are disposed on the second surface, and a connection node of the first feed branch and the radiating element is a first feed point, and the connection node of the second feed branch and the radiating element is a second feed point; the radiating element is provided with a first groove and a second groove.

Abstract: An electronic device includes a display layer in which an active region and a peripheral region proximate to the active region are defined and a controller that is configured to control the display layer. The display layer includes a plurality of pixels, a plurality of antenna patterns that transmit and receive a first signal having a predetermined frequency, and a switch connected to at least one of the plurality of antenna patterns. The controller provides, to the switch, a control signal to control the switch. The switch includes a first line to which a ground voltage is provided, a second line that is floated, a third line to which the first signal is provided, and a fourth line connected to the at least one of the plurality of antenna patterns and electrically connected to the first line, the second line, or the third line based on the control signal.

Abstract: One aspect of the present disclosure is to provide a connector enabling good heat dissipation. A connector 11 according to the one aspect of the present disclosure is provided with a housing 13 made of metal, a flat plate-like busbar 14 to be held in the housing 13, a ceramic member 20 to be interposed between one flat surface 14a of the busbar 14 and a contact portion 19 of the housing 13, and compression coil springs 21 for pressing another flat surface 14b of the busbar 14 toward the contact portion 19.

Abstract: A semiconductor device includes a substrate, an active fin on the substrate, and a transistor on the active fin. The transistor includes a lower channel layer, an intermediate channel layer, and an upper channel layer sequentially stacked, and a gate structure traversing the active fin, respectively surrounding the channel layers, and including a gate dielectric and a gate electrode. The gate electrode includes a lower electrode portion between the active fin and the lower channel layer, an intermediate electrode portion between the lower channel layer and the intermediate channel layer, and an upper electrode portion between the intermediate channel layer and the upper channel layer. The gate electrode includes a work function adjusting metal element, and a content of the work function adjusting metal element in the lower electrode portion is different from that in each of the intermediate electrode portion and the upper electrode portion.

Abstract: A semiconductor structure includes a substrate and a semiconductor channel layer over the substrate. The semiconductor structure includes a high-k gate dielectric layer over the semiconductor channel layer, a work function metal layer over the high-k gate dielectric layer, and a bulk metal layer over the work function metal layer. The work function metal layer includes a first portion and a second portion over the first portion. Both the first portion and the second portion are conductive. Materials included in the second portion are also included in the first portion. The first portion is doped with silicon at a first dopant concentration, and the second portion is not doped with silicon or is doped with silicon at a second dopant concentration lower than the first dopant concentration.

Abstract: A semiconductor device includes a substrate, an isolation structure on the substrate, a fin protruding from the substrate and through the isolation structure, a gate stack engaging the fin, and a gate spacer on sidewalls of the gate stack. The gate spacer includes an inner sidewall facing the gate stack and an outer sidewall opposing the inner sidewall. The inner sidewall has a first height measured from a top surface of the fin and a bowed structure in a top portion of the inner sidewall. The bowed structure extends towards the gate stack for a first lateral distance measured from a middle point of the inner sidewall. The first lateral distance is less than about 8% of the first height.

Abstract: A method includes forming source/drain regions in a semiconductor substrate; depositing a zirconium-containing oxide layer over a channel region in the semiconductor substrate and between the source/drain region; forming a titanium oxide layer in contact with the zirconium-containing oxide layer; forming a top electrode over the zirconium-containing oxide layer, wherein no annealing is performed after depositing the zirconium-containing oxide layer and prior to forming the top electrode.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate, a conductive feature on the substrate, and an electrical connection structure on the conductive feature. The electrical connection includes a first grain made of a first metal material, and a first inhibition layer made of a second metal layer that is different than the first metal material. The first inhibition layer extends vertically along a first side of a grain boundary of the first grain and laterally along a bottom of the grain boundary of the first grain.

Abstract: A semiconductor device includes a first device configured to receive a first level voltage through a first terminal, and output a first output voltage through a second terminal when a gate voltage is applied through a gate terminal; a boost device configured to receive a second level voltage through a first terminal, and output a second output voltage having a higher value than the first output voltage when the first output voltage is applied as a gate voltage through a gate terminal; and a second device configured to receive a third level voltage through a first terminal, and output a third output voltage when the second output voltage is applied as a gate voltage through a gate terminal, wherein the second output voltage is greater than a threshold voltage of the second device.

Abstract: A light detecting device includes: a filter array including filters two-dimensionally arrayed and an image sensor including light detection elements. Each of first and second filters included in the filters includes a first reflective layer, a second reflective layer, and an intermediate layer therebetween and has a resonance structure having resonant modes whose orders are different from each other. A refractive index and/or a thickness of the intermediate layer in the first and second filters is different depending on the filter. A transmission spectrum of each of the first and second filters has local maximum value of transmittance at each of wavelengths included in a wavelength region, and the wavelengths correspond to the resonant modes, respectively. The image sensor is disposed at a position where the image senor receives passing light that passes through the filter array, to detect components in the wavelengths included in the passing light.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method includes forming a first dielectric bonding layer over a first dielectric structure, which is disposed on a first substrate and surrounds a first plurality of interconnects. The first dielectric bonding layer is patterned to form a first recess exposing one of the first plurality of interconnects. A first conductive bonding segment is formed within the first recess. A second dielectric bonding layer is formed over a TSV extending through a second substrate. The second dielectric bonding layer is patterned to form a second recess exposing the TSV. A second conductive bonding segment is formed within the second recess. The first substrate is bonded to the second substrate along an interface comprising dielectric and conductive regions. The conductive region includes a conductive interface between the first and second conductive bonding segments.

Abstract: A light emitting device substrate includes an insulating layer, a plurality of upper pads spaced apart from each other in a matrix pattern on the insulating layer, a first circuit pattern inside the insulating layer, the first circuit pattern electrically connecting some of the plurality of upper pads to each other, a second circuit pattern inside the insulating layer, the second circuit pattern being under the first circuit pattern and electrically connected to the first circuit pattern, and a plurality of lower pads spaced apart from each other under the insulating layer, a number of the plurality of lower pads being smaller than a number of the plurality of upper pads, and at least one of the plurality of lower pads being electrically connected to two or more upper pads of the plurality of upper pads via the first circuit pattern and the second circuit pattern.

Abstract: A circuit suitable for use with a multi-level power converter cell that (1) charges boot capacitors at startup to a sufficient level to power level shifters and drivers that control the power switches within the cell, (2) pre-charges each fly capacitor to a target voltage, (3) provides a shut-down and/or a standby mode of operation that enables a quick re-start of operation, and (4) balances fly capacitor voltages when the fly capacitor(s) is/are not actively charge-balanced. One embodiment includes a first switchable current source coupled between a fly capacitor and an input voltage; a second switchable current source coupled between the fly capacitor and a reference potential; and a third switchable current source coupled in parallel with the fly capacitor; wherein the switchable current sources are configured to charge the fly capacitor in a first mode of operation, and to discharge the fly capacitor in a second mode of operation.