Abstract: A scalable N×N single-chip dual-band MIMO RF transceiver module compatible with the IEEE 802.11n standard for WLAN applications is provided. A modular design approach allows a transceiver of substantially any dimension to be created on a single chip that may be easily integrated with other system components. An N×N MIMO transceiver module includes N substantially identical transceiver blocks and a common local oscillator. Each transceiver block includes transmitters and receivers for transmitting and receiving signals in two distinct frequency bands. The transceiver blocks further include one or more local oscillator signal repeaters for receiving one or more local oscillator signals and forwarding the one or more local oscillator signals to subsequent transceiver blocks.
Type:
Grant
Filed:
September 22, 2008
Date of Patent:
March 20, 2012
Assignee:
Marvell International Ltd.
Inventors:
Sang Won Son, Paolo Rossi, Siu Chuang Lu
Abstract: A system and method for switching a mode of a receiver between a monophonic and stereophonic mode is disclosed. The method can include generating a residual signal indicative of a noise level associated with a pilot energy signal, calculating a residual block energy level of the residual signal over an observation interval, generating a monitor signal based on a number of times the pilot energy signal is less than a pilot energy threshold during the observation interval and switching the mode of the receiver based on the residual block energy level and the monitor signal.
Abstract: A coding system for digital data. The coding system includes a constrained encoder module configured to generate encoded data based on a first constrained code; a bit insertion module configured to insert at least one bit location in the encoded data; and an inner encoding module configured to (i) generate inner-code parity bits based on the encoded data, and (ii) program the inner-code parity bits into the at least one bit location.
Abstract: A method and device for compensating for undesirable signal characteristics such as baseline wander that includes a linear equalization filter responsive to receive an input, a combiner responsive to an output of the linear equalization filter, and a decision feedback equalization filter responsive to an output of the combiner, where the combiner is further responsive to an output of the decision feedback equalizer. Additionally, an error feedback circuit is responsive to the output of the combiner, and the combiner is further responsive to an output of the error feedback circuit to form a compensated signal having reduced distortion relative to the distorted signal.
Abstract: A system includes a linked-list generator module that generates a linked list of tones based on tones and bit loads of the respective tones in a digital subscriber line (DSL) communication system, a trellis encoder module that encodes data bits associated with respective ones of the tones, and a bit application module that communicates the data bits to the trellis encoder module based on the linked list.
Type:
Grant
Filed:
August 23, 2007
Date of Patent:
March 20, 2012
Assignee:
Marvell International Ltd.
Inventors:
Peter Tze-Hwa Liu, Jacky S. Chow, Yi Han, Fay Yew
Abstract: A method comprises terminating transmission of a first frame having a first class of service when a transmission failure is detected, incrementing an attempt count for the first class of service, transmitting a second frame having a second class of service before retransmitting the first frame if the second class of service is higher than the first class of service, and discarding pending frames for the first class of service when at least one of the attempt count exceeds a predetermined attempt threshold and the first class of service falls below a predetermined discard threshold.
Abstract: A storage system comprises a linear block encoder. A write circuit writes an output of the linear block encoder to a storage medium. A read circuit reads data from the storage medium. A channel decoder decodes the data. A soft linear block code decoder that decodes the data decoded by the channel decoder. The channel decoder decodes the data read in a first iteration. In a subsequent iteration the channel decoder decodes the data read by the read circuit and utilizes information decoded by the soft linear block code decoder. A threshold check circuit selects an output of the soft linear block code decoder if a number of parity check violations has a first relationship with respect to a threshold, or an output of the channel decoder if the number of parity check violations has a second relationship with respect to the threshold.
Abstract: A processor includes a first level of cache memory and a first set of instructions configured to implement a first cache coherency protocol. The processor also includes a second set of instructions configured to implement a second cache coherency protocol and a cache coherency protocol selector having at least two choice-states. The processor further includes a cache coherency implementer configured to implement the first cache coherency protocol or the second cache coherency with respect to the first level of cache memory based on a selected choice-state of the cache coherency protocol selector.
Type:
Grant
Filed:
April 1, 2009
Date of Patent:
March 13, 2012
Assignee:
Marvell International Ltd.
Inventors:
R. Frank O'Bleness, Sujat Jamil, David E. Miner, Joseph Delgross, Tom Hameenanttila, Jeffrey Kehl
Abstract: In one or more embodiments, a method, computer-readable media, system and or modules are capable of generating an address for a multimedia data block included in a stream of multimedia data. The address can be maintained in one or more local registers. The one or more local registers can be linked to one or more processor registers associated with a processor to synchronize communication of the stream of multimedia data with the processor.
Type:
Grant
Filed:
November 13, 2008
Date of Patent:
March 13, 2012
Assignee:
Marvell International Ltd.
Inventors:
Moinul H. Khan, Mark N. Fullerton, Bradley C. Aldrich, Anitha Kona
Abstract: An image processing method and device for processing multiple rows of pixels of an image simultaneously with a single instruction. The processing includes selecting a pixel window having a plurality of pixels of an image spanning across multiple rows and columns, building vertical and horizontal load registers to include the plurality of pixels of the selected pixel window, and simultaneously processing selected pixels of the plurality of pixels included in the vertical and horizontal load registers using a single instruction, wherein the vertical and horizontal load registers are shifted when the selected pixels are processed. Accordingly, a method and device for efficient processing of an image is provided.
Abstract: Some of the embodiments of the present disclosure provide a method for programming a flash memory having a plurality of memory blocks, wherein each memory block of the plurality of memory blocks is either a single-level cell (SLC) memory block or a multi-level cell (MLC) memory block, the method comprising assigning a weighting factor to each memory block of the plurality of memory blocks based on whether the memory block is an SLC memory block or an MLC memory block, tracking a number of write—erase cycles for each memory block, and selecting one or more memory blocks for writing data based at least in part on the weighting factor and the tracked number of write—erase cycles of each memory block of the plurality of memory blocks. Other embodiments are also described and claimed.
Abstract: Reproduction of encoded data which includes a split-mark. FIR data corresponding to split-mark and FIR data affected by the split-mark due to inter-symbol-interference are identified. FIR data corresponding to the split-mark is removed from the received FIR data. Recovered data is created by removing incorrect inter-symbol-interference from the FIR data due to the split-mark, and adding correct inter-symbol-interference from codeword bits. The recovered data is stitched together with data unaffected by split-mark data.
Abstract: A system and method of beamforming may reduce feedback requirements. In some implementations, a beamforming technique may employ a diagonal matrix as a beamforming matrix along with a stream-to-transmit antenna mapping matrix. In some antenna phase beamforming strategies, a diagonal beamforming matrix in which the diagonal elements have a constant magnitude may be employed. Accordingly, a beamforming system may be utilized with few feedback information bits being transmitted from the beamformee; such a system may also minimize or eliminate power fluctuations among multiple transmit antennae.
Type:
Grant
Filed:
April 3, 2008
Date of Patent:
March 6, 2012
Assignee:
Marvell International Ltd.
Inventors:
Jungwon Lee, Rohit U. Nabar, Hui-Ling Lou
Abstract: A data processing system, apparatus and method for performing fractional multiply operations is disclosed. The system includes a memory that stores instructions for SIMD operations and a processing core. The processing core includes registers that store operands for the fractional multiply operations. A coprocessor included in the processing core performs the fractional multiply operations on the operands and stores the result in a destination register that is also included in the processing core.
Abstract: Systems and methods are provided for automatically setting up an initial configuration of a wireless repeater and managing one or more wireless repeaters in a wireless local area network.
Type:
Grant
Filed:
October 8, 2004
Date of Patent:
March 6, 2012
Assignee:
Marvell International Ltd.
Inventors:
James Chieh-Tsung Chen, Chor-Teck Law, Brian Bosso, May Chiang
Abstract: A method and apparatus for processing a frequency domain digital Orthogonal Frequency Division Multiplexing (OFDM) symbol. The method includes generating an estimate of a channel for each sub-carrier of the frequency domain digital OFDM symbol; generating a plurality of demodulated symbols based, at least in part on, the estimate of the channel for each sub-carrier, in which each demodulated symbol corresponding to a given sub-carrier of the frequency domain digital OFDM symbol; calculating a decision metric for each sub-carrier based on (i) the channel estimate corresponding to the sub-carrier and (ii) the demodulated symbol corresponding to the sub-carrier; and estimating a most likely transmitted symbol for each sub-carrier of the frequency domain digital OFDM symbol based on the decision metric corresponding to the sub-carrier.
Abstract: A plurality of phases are determined. The plurality of phases are to be applied to a plurality of transmit signals to be transmitted via a plurality of transmit antennas. Each transmit signal comprises a plurality of sub-carriers. Each phase of the plurality of phases is to be applied to a corresponding block of sub carriers in the plurality of transmit signals, and each block of sub-carriers comprises a plurality of sub-carriers that are adjacent in frequency. The plurality of phases are applied to the plurality of transmit signals to implement transmit diversity. Each phase is applied to the corresponding block of sub carriers in the plurality of transmit signals.
Type:
Grant
Filed:
May 29, 2008
Date of Patent:
March 6, 2012
Assignee:
Marvell International Ltd.
Inventors:
Jungwon Lee, Jihwan P. Choi, Hui-Ling Lou, Rohit U. Nabar, Yakun Sun
Abstract: A system and method of laser bias control in optical recording media applications are disclosed. In some implementations, bias control for output power may be based upon a detected ratio of erase power to write (or peak) power, i.e., the Pe/Pw (or Epsilon, ?) ratio.
Abstract: Systems and methods are provided for implementing list decoding in a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. The soft-information can be organized into an order of combinations of error events for list decoding. An RS decoder can employ a list decoder that uses a pipelined list decoder architecture. The list decoder can include one or more syndrome modification circuits that can compute syndromes in parallel. A long division circuit can include multiple units that operate to compute multiple quotient polynomial coefficients in parallel. The list decoder can employ iterative decoding and a validity test to generate error indicators. The iterative decoding and validity test can use the lower syndromes.
Type:
Grant
Filed:
August 14, 2009
Date of Patent:
March 6, 2012
Assignee:
Marvell International Ltd.
Inventors:
Siu-Hung Fred Au, Gregory Burd, Zining Wu, Jun Xu, Ichiro Kikuchi, Tony Yoon
Abstract: The hand-held printer includes a print module configured for multidirectional printing, a print head in communication with the print module. The print head includes a plurality of nozzle arrays and wherein the nozzles in each of the plurality of nozzle are disposed substantially equidistant from a reference point. The hand-held printer further includes a circular cap configured to rotatably cooperate with the print head, wherein the circular cap cooperates with the print head to define a seal when the circular cap is disposed in a closed position.