Abstract: A method for pretreating a solder surface for fluxless soldering is disclosed. The method uses a noble fluorine gas to remove surface oxides from solder surfaces, without the use of external stimulation. A noble fluorine gas is suffused across the solder surface to reduce or eliminate or chemically convert the surface oxides. The process can take place at atmospheric pressure and room temperature. A simple belt driven transport may be used to move the parts past a nozzle which emits the vapor in a system similar to a conventional solder reflow machine.

Abstract: A field effect transistor includes a pair of buried centroid regions in a semiconductor substrate at a predetermined depth from the substrate face and having a doping concentration opposite the source and drain regions. A gradient region surrounds each of the pair of buried centroid regions. The gradient regions have decreasing doping concentration in all directions away from the associated centroid region. Source and drain extension regions may also be provided. The buried centroid/gradient regions operate to screen charge on the source and drain regions facing the channel to prevent this charge from interacting with the channel. Short channel effects are thereby reduced or minimized. The threshold voltage of the device can also be adjusted without the need for threshold adjusting implants. The buried centroid/gradient regions and source and drain extension regions may be fabricated in a self-aligned process using the gate and gate sidewall spacers as a mask.

Abstract: A fluxless soldering sample pretreating system includes a sample chamber having an opening therein and a sample holder. A sample chamber extension extends outwardly from the opening to define a passageway from the sample chamber extension, through the opening, and into the sample chamber. A fluorine-containing gas is supplied into the sample chamber extension. Am energy source such as a microwave oven surrounds the sample chamber extension. The microwave oven produces microwave energy in the sample chamber extension to form a plasma therein and dissociate the fluorine-containing gas into atomic fluorine. A perforated aluminum plate extends transversely across the passageway and blocks the plasma from traversing the passageway from the sample chamber extension into the sample chamber, while allowing the atomic fluorine to traverse the passageway from the sample chamber extension into the sample holder.

Abstract: An electrically and mechanically robust microelectromechanical transducer is formed of a pleated dielectric sheet having patterned electrical conductors on the opposing faces thereof. The pleats define a plurality of spaced apart walls, with each wall including an electrically conductive portion at one side thereof. Positive and negative voltages, applied to opposite faces of the pleated sheet, cause the walls to move towards one another by electrostatic attraction. The walls can also move away from one another by electrostatic repulsion upon application of appropriate voltages. The microelectromechanical transducer may be fabricated by fabricating a sheet with integral pleats or by forming a "self-pleating" flat sheet which forms pleats after conductor fabrication thereon.

Abstract: A vertical microelectronic field emitter includes a conductive top portion and a resistive bottom portion in an elongated column which extends vertically from a horizontal substrate. An emitting electrode may be formed at the base of the column, and an extraction electrode may be formed adjacent the top of the column. The elongated column reduces the parasitic capacitance of the microelectronic field emitter to provide high speed operation, while providing uniform column-to-column resistance. The field emitter may be formed by first forming tips on the face of a substrate and then forming trenches in the substrate around the tips to form columns in the substrate, with the tips lying on top of the columns. The trenches are filled with a dielectric and a conductor layer is formed on the dielectric. Alternatively, trenches may be formed in the face of the substrate with the trenches defining columns in the substrate. Then, tips are formed on top of the columns.

Abstract: A defective area on a microelectronic substrate is repaired using an image reversal photoresist and image reversal process. The defective area on a microelectronic substrate is identified and a layer of image reversal photoresist is applied to the microelectronic substrate. The image reversal photoresist is then exposed twice in an image reversal process, and the image reversal photoresist is then removed over the defective area. A repair material is then blanket deposited, and the image reversal photoresist is removed in a lift-off operation such that the material on the defective area remains. Missing lines and broken lines may be repaired. Conductive and dielectric materials may be repaired.

Abstract: A flat panel display includes a ferroelectric thin film between first and second spaced apart electrodes. The ferroelectric thin film emits electrons upon application of a predetermined voltage between the first and second spaced apart electrodes. The electrons are emitted in an electron emission path and impinge upon a luminescent layer such as a phosphor layer, which produces luminescence upon impingement upon the emitter electrodes. The ferroelectric thin film is preferably about 2 .mu.m or less in thickness and is preferably a polycrystalline ferroelectric thin film. More preferably, the thin ferroelectric film is a highly oriented, polycrystalline thin ferroelectric film. Most preferably, highly oriented ferroelectric thin film has a preferred (001) crystal orientation and is about 2 .mu.m or less in thickness. A flat panel display may be formed of arrays of such display elements. Top and bottom electrodes or side electrodes may be used.

Abstract: A method of forming a metal-disilicide (MSi.sub.2) film from a silicon-on-insulator (SOI) substrate having an insulating underlayer and a silicon outerlayer includes the formation of a first capping layer on a portion of the silicon outerlayer. The first capping layer preferably includes titanium and a preselected metal (M) such as cobalt. A step is then performed to convert a first portion of the silicon outerlayer to metal-disilicide. This step is preferably accomplished by a rapid thermal annealing step. Thereafter, a second capping layer is formed on the metal-disilicide layer. The second capping layer preferably includes titanium and metal-monosilicide (MSi). Next, a step is performed to convert a second portion of the silicon outerlayer, beneath the first portion, to metal-disilicide while preventing phase-reversal of the already formed metal-disilicide layer to metal-monosilicide. This step is preferably accomplished by a rapid thermal annealing step as well.

Abstract: A temporary substrate for solder bumps may be used to transfer solder bumps to a microelectronic device. The temporary substrate includes a solder nonwettable surface and a plurality of conductive vias therein. A solder bump is formed on each of the conductive vias and is electrically and mechanically connected thereto. The solder bump extends over the solder nonwettable surface to produce a solder bump cross-sectional area which is greater than the cross-sectional area of the conductive via. A microelectronic device is placed adjacent the temporary substrate with each input/output pad adjacent a respective solder bump. An electrical and mechanical connection is formed between the solder bump and the input/output pad, and the microelectronic device is separated from the temporary substrate with the solder bump remaining connected to the input/output pad. The temporary substrate can also be used for burn-in and testing of microelectronic devices and rework on multichip modules.

Abstract: A microelectromechanical transducer including a plurality of parallel electrically conductive strips maintained in closely spaced relation by a plurality of spacers can generate useful displacements and forces. The transducer can be strengthened by arranging the conductive strips in cells surrounded by unidirectional cell stiffening members and unidirectional displacement limiting members. The unidirectional cell stiffening members may include notches. The unidirectional displacement limiting members may include unidirectional buckling straps or flexible arches. The cells of electrically conductive strips can be organized in modular or fractal arrays.

Abstract: An electrical connector includes a housing and a row of connector contacts coupled to the housing. The row of connector contacts has a predetermined center-to-center spacing between adjacent contacts, with the predetermined center-to-center spacing being relatively large relatively far from an imaginary reference point in the row of connector contacts, and being relatively small relatively near the imaginary reference point in the row of connector contacts. The imaginary reference point is preferably at the center of the row of contacts, and the center-to-center contact spacing preferably progressively increases from the center of the row to the ends of the row. The size of the connector contacts may also progressively increase as well. The electrical connector is preferably adapted for use with a multilayer ceramic substrate which includes a row of capture pads of the same predetermined center-to-center spacing at the edge thereof.

Abstract: A method of soldering a copper layer without the use of fluxing agents by exposing the copper layer to a fluorine-containing plasma. Solder is then placed onto the surface of the copper layer and reflowed. Reflow can take place at low temperatures, atmospheric pressure and in an inert or oxidizing atmosphere using standard solder reflow equipment.

Abstract: An integrated circuit chip having solder bumps thereon may be tested using a temporary substrate having substrate pads corresponding to locations of the input/output pads on the chip and having a sacrificial conductor layer on the temporary substrate pads. The solder bumps are placed adjacent the corresponding sacrificial metal layer and heated to form an electrical and mechanical connection between the chip and the temporary substrate. The chip is then tested and/or burned-in on the temporary substrate. After testing/burn-in, the sacrificial metal layer is dissolved into the solder bumps by heating. The integrated circuit chip, including a solder bump having the dissolved sacrificial metal layer therein, may be easily removed from the temporary substrate. Solder bumps may also be formed on the temporary substrate and transferred to unbumped chips.

Abstract: An integrated circuit chip having solder bumps thereon may be tested using a temporary substrate having substrate pads corresponding to locations of the input/output pads on the chip and having a sacrificial conductor layer on the temporary substrate pads. The solder bumps are placed adjacent the corresponding sacrificial metal layer and heated to form an electrical and mechanical connection between the chip and the temporary substrate. The chip is then tested and/or burned-in on the temporary substrate. After testing/burn-in, the sacrificial metal layer is dissolved into the solder bumps by heating. The integrated circuit chip, including a solder bump having the dissolved sacrificial metal layer therein, may be easily removed from the temporary substrate. Solder bumps may also be formed on the temporary substrate and transferred to unbumped chips.

Abstract: A vertical microelectronic field emitter includes a conductive top portion and a resistive bottom portion in an elongated column which extends vertically from a horizontal substrate. An emitter electrode may be formed at the base of the column, and an extraction electrode may be formed adjacent the top of the column. The elongated column reduces the parasitic capacitance of the microelectronic field emitter to provide high speed operation, while providing uniform column-to-column resistance. The field emitter may be formed by first forming tips on the face of a substrate and then forming trenches in the substrate around the tips to form columns in the substrate, with the tips lying on top of the columns. The trenches are filled with a dielectric and a conductor layer is formed on the dielectric. Alternatively, trenches may be formed in the face of the substrate with the trenches defining columns in the substrate. Then, tips are formed on top of the columns.

Abstract: A high performance integrated circuit chip package includes a support substrate having conductors extending from one face to the opposite face thereof and a multilayer wiring substrate on the opposite face of the support substrate for connecting chips mounted thereon to one another and to the conductors. A heat sink includes microchannels at one face thereof, with thermally conductive cushions connecting the one face of the heat sink with the exposed back sides of the chips, to provide a high density chip package with high heat dissipation. The support substrate and heat sink may be formed of blocks of material having thermal expansion matching silicon. The cushions are a low melting point solder, preferably pure indium, and are sufficiently thick to absorb thermal stresses, but sufficiently thin to efficiently conduct heat from the chips to the heat sink.

Abstract: Capture pads of variable size are provided on the face of a multilayer ceramic substrate, to accommodate the actual shrinkage tolerance of the substrate at each capture pad position. For example, assuming a minimum shrinkage reference point is at the center of the substrate face, the capture pad size is relatively large adjacent the edges of the substrate face and relatively small adjacent the center of the substrate face. By sizing each capture pad based on the maximum positional variation at the particular capture pad position, higher contact density is obtainable than with known uniform size capture pads. The variable size capture pads may also be used at one or more rows of capture pads located along one or more edges of the substrate, for electrical connection to an edge connector. For example, assuming a minimum shrinkage reference point at the center of the row, the capture pads are relatively large adjacent the ends of the row of capture pads and are relatively small adjacent the center of the row.

Abstract: The base of solder bumps is preserved by converting the under-bump metallurgy between the solder bump and contact pad into an intermetallic of the solder and the solderable component of the under-bump metallurgy prior to etching the under-bump metallurgy. The intermetallic is resistant to etchants which are used to etch the under-bump metallurgy between the contact pads. Accordingly, minimal undercutting of the solder bumps is produced, and the base size is preserved. The solder may be plated on the under-bump metallurgy over the contact pad through a patterned solder dam layer having a solder accumulation region thereon. The solder dam is preferably a thin film layer which may be accurately aligned to the underlying contact pad to confine the wetting of the molten solder during reflow. Misalignment between the solder bump and contact pad is thereby reduced. The solder bumps so formed include an intermetallic layer which extends beyond the bump to form a lip around the base of the bump.

Abstract: A microelectromechanical transducer including a plurality of strips arranged in an array and maintained in a closely spaced relation by a plurality of spacers. An electrically conductive layer on portions of the strips and spacers distributes electrical signal within the transducer to cause adjacent portions of the strips to move together. The strips and spacers may be formed from a common dielectric layer using microelectronic fabrication techniques. Two transducers may be coupled at an angle offset from parallel for two-dimensional micropositioning. A photodetector and Fresnel lens may be combined with the micropositioner using the transducers for optical scanning microscopy.

Abstract: An integrated circuit chip having solder bumps thereon may be tested using a temporary substrate having substrate pads corresponding to locations of the input/output pads on the chip and having a sacrificial conductor layer on the temporary substrate pads. The solder bumps are placed adjacent the corresponding sacrificial metal layer and heated to form an electrical and mechanical connection between the chip and the temporary substrate. The chip is then tested and/or burned-in on the temporary substrate. After testing/burn-in, the sacrificial metal layer is dissolved into the solder bumps by heating. The integrated circuit chip, including a solder bump having the dissolved sacrificial metal layer therein, may be easily removed from the temporary substrate. Solder bumps may also be formed on the temporary substrate and transferred to unbumped chips.