Abstract: A network-connected device includes at least one communication port, packet processing circuitry and Diagnostics Direct Memory Access (DMA) Circuitry (DDC). The at least one communication port is configured to communicate packets over a network. The packet processing circuitry is configured to receive, buffer, process and transmit the packets. The DDC is configured to receive a definition of (i) one or more diagnostic events, and (ii) for each diagnostic event, a corresponding list of diagnostic data that is generated in the packet processing circuitry and that pertains to the diagnostic event, and, responsively to occurrence of a diagnostic event, to gather the corresponding list of diagnostic data from the packet processing circuitry.

Abstract: An optical switching device (20) includes a substrate (39) and first and second optical waveguides (23, 25) having respective first and second tapered ends (62, 64), which are fixed on the substrate in mutual proximity one to another. A pair of electrodes (36, 38) is disposed on the substrate with a gap therebetween. A cantilever beam (32) is disposed on the substrate within the gap and configured to deflect transversely between first and second positions within the gap in response to a potential applied between the electrodes. A third optical waveguide (21) is mounted on the cantilever beam and has a third tapered end (60) disposed between the first and second tapered ends of the first and second waveguides, so that the third tapered end is in proximity with the first tapered end when the cantilever beam is in the first position and is in proximity with the second tapered end when the cantilever beam is in the second position.

Abstract: A network device includes an enclosure, a multi-chip module (MCM), an optical-to-optical connector, and a multi-core fiber (MCF) interconnect. The enclosure has a panel. The MCM is inside the enclosure. The optical-to-optical connector, which is mounted on the panel of the enclosure, is configured to transfer a plurality of optical communication signals. The MCF interconnect includes multiple fiber cores for routing the plurality of optical communication signals between the MCM and the panel. The MCF has a first end at which the multiple fiber cores are coupled to the MCM, and a second end at which the multiple fiber cores are connected to the optical-to-optical connector on the panel.

Abstract: Embodiments are disclosed for generating an optical Pulse Amplitude Modulation 4-level (PAM-4) signal from bandwidth-limited duobinary electrical signals in a Mach-Zehnder modulator. An example system includes an MZM structure that comprises a first waveguide interferometer arm structure associated with a first semiconductor device and a second waveguide interferometer arm structure associated with a second semiconductor device. A polybinary electrical signal is applied to or between the first semiconductor device and the second semiconductor device to convert an input optical signal provided to the MZM structure into an optical PAM-4 signal.

Abstract: A bi-directional fan device that is field replaceable within an electronic system is provided. The bi-directional fan device includes a fan unit that cools an electronic system when connected to a power source, and an electrical connector constructed at both ends of the fan unit to electrically connect to the power source.

Abstract: A method including providing a SHARP tree including a plurality of data receiving processes and at least one aggregation node, designating a data movement command, providing a plurality of data input vectors to each of the plurality of data receiving processes, respectively, the plurality of data receiving processes each passing on the respective received data input vector to the at least one aggregation node, and the at least one aggregation node carrying out the data movement command on the received plurality of data input vectors. Related apparatus and methods are also provided.

Abstract: A network device includes at least one port, a memory, data-path circuitry, and a processor. The at least one port is to exchange packets with a network. The data-path circuitry is to process the packets. The memory is to store signatures of traffic patterns according to a locality-sensitive signature function., and corresponding parameter settings for the data-path circuitry. The processor is to assess a current traffic pattern of the packets, to calculate a current signature over the current traffic pattern using the locality-sensitive signature function, to query the memory using the current signature, to configure the data-path circuitry, in response to finding a stored signature that is within a specified distance from the current signature, with a parameter setting that corresponds to the found signature, and take an alternative action in response to finding that no stored signature is within the specified distance from the current signature.

Abstract: A network element includes circuitry and multiple ports. The multiple ports are configured to connect to a communication network. The circuitry is configured to receive via one of the ports a packet that originated from a source node and is destined to a destination node, the packet including a mark that is indicative of a cumulative state derived from at least bandwidth utilization conditions of output ports that were traversed by the packet along a path, from the source node up to the network element, to select a port for forwarding the packet toward the destination node, to update the mark of the packet based at least on a value of the mark in the received packet and on a local bandwidth utilization condition of the selected port, and to transmit the packet having the updated mark to the destination node via the selected port.

Abstract: A method for communication includes receiving in a network device work requests posted by a host processor to perform a series of communication transactions, including at least a first transaction and a second transaction comprising first and second operations to be executed in a sequential order in response to corresponding first and work requests posted by the host processor. In response to the work requests, data packets are transmitted over a network from the network device to a destination node and corresponding responses are received from the destination node. Based on the received responses, completion of the first operations in the first transaction is reported from the network device to the host processor according to the sequential order, and completion of the second operation in the second transaction is reported from the network device to the host processor regardless of whether the first transaction has been completed.

Abstract: Computing apparatus includes a host computer, including at least first and second host bus interfaces. A network interface controller (NIC) includes a network port, for connection to a packet communication network, and first and second NIC bus interfaces, which communicate via first and second peripheral component buses with the first and second host bus interfaces, respectively. Packet processing logic, in response to packets received through the network port, writes data to the host memory concurrently via both the first and second NIC bus interfaces in a sequence of direct memory access (DMA) transactions, and after writing the data in any given DMA transaction, writes a completion report to the host memory with respect to the given DMA transaction while verifying that the completion report will be available to the CPU only after all the data in the given DMA transaction have been written to the host memory.

Abstract: An authentication method, network switch, and network device are provided. In one example, a method is described that includes receiving a first signal indicative of a data lane being activated and configured to carry data to or within the network switch, receiving a second signal indicative of an authentication lane being established in the network switch or a device connected to the network switch, where the authentication lane is different from the data lane, and enabling data transmission across the data lane only in response to receiving the second signal indicative of the authentication lane being established.

Abstract: A network adapter includes a network interface, a host interface and processing circuitry. The network interface is configured to connect to a communication network. The host interface is configured to communicate with a host processor running multiple application programs. The processing circuitry includes one or more bandwidth-control policers, and is configured to receive from the communication network a packet destined to a given application program among the application programs running on the host processor, to associate a bandwidth-control policer with the packet, selected from among the bandwidth-control policers, and to apply the selected bandwidth-control policer to the packet to produce a policer result.

Abstract: A connector for a networking cable assembly includes a substrate, a first set of contacts on a first surface of the substrate that electrically connect to leads of a first cable, and a second set of contacts on the first surface of the substrate that electrically connect to leads of a second cable. The first set of contacts are spaced apart from the second set of contacts in a first direction by an amount that enables the second cable to be stacked on the first cable and passed over the first set of contacts to electrically connect to the leads of the second cable.

Abstract: Several VCSEL devices for long wavelength applications in wavelength range of 1200-1600 nm are described. These devices include an active region between a semiconductor DBR on a GaAs wafer and a dielectric DBR regrown on the active region. The active region includes multi-quantum layers (MQLs) confined between the active n-InP and p-InAlAs layers and a tunnel junction layer above the MQLs. The semiconductor DBR is fused to the bottom of the active region by a wafer bonding process. The design simplifies integrating the reflectors and the active region stack by having only one wafer bonding followed by regrowth of the other layers including the dielectric DBR. An air gap is fabricated either in an n-InP layer of the active region or in an air gap spacer layer on top of the semiconductor DBR. The air gap enhances optical confinement of the VCSEL. The air gap may also contain a grating.

Abstract: One embodiment includes data communication apparatus including a storage sub-system to be connected to storage devices, and processing circuitry to manage transfer of content with the storage devices over the storage sub-system responsively to content transfer requests, while pacing commencement of serving of respective ones of the content transfer requests responsively to availability of spare data capacity of the storage sub-system, find a malfunctioning storage device currently assigned a given data capacity of the storage sub-system and currently assigned to serve at least one content transfer request, and reallocate the given data capacity of the storage sub-system currently assigned to the malfunctioning storage device for use by at least another one of the storage devices while the at least one content transfer request assigned to be served by the malfunctioning storage device is still awaiting completion by the malfunctioning storage device.

Abstract: Optical splitting adaptors and associated methods of manufacturing are provided. An example optical splitting adaptor includes a first connector housing that interfaces with a first optical transceiver having a first data rate, and the first connector housing accommodates a first type multi-fiber ferrule of a first number of fibers. The example optical splitting adaptor also includes a second connector housing that defines dual receptacles for interfacing with a second optical transceiver and a third optical transceiver, and the dual receptacles receive respective multi-fiber ferrules. The example optical splitting adaptor further includes a plurality of fibers operably connecting the first connector housing and the second connector housing such that, in operation, the plurality of fibers perform optical splitting between the first type multi-fiber ferrule of the first connector housing and the multi-fiber ferrules received by the dual receptacles of the second connector housing.

Abstract: A synchronized communication system includes a plurality of network communication devices, one of which is designated as a root device and the others designated as slave devices. Each network communication device includes one or more ports and communications circuitry, which processes the communication signals received by the one or more ports so as to recover a respective remote clock from each of the signals. A synchronization circuit is integrated in the root device and provides a root clock signal, which is conveyed by clock links to the slave devices. A host processor selects one of the ports of one of the network communication devices to serve as a master port, finds a clock differential between the root clock signal and the respective remote clock recovered from the master port, and outputs, responsively to the clock differential, a control signal causing the synchronization circuit to adjust the root clock signal.

Abstract: A network node includes a port and circuitry. The port is configured for communicating over a packet network. The circuitry is configured to receive, via the port, a sequence of packets from a peer network node, the sequence of packets including (i) a time-protocol packet and (ii) a transmit-side (TX) time-stamp indicative of a time at which the time-protocol packet was transmitted from the peer network node, to assess a receive-side (RX) traffic pattern over one or more of the received packets in the sequence that precede reception of the time-protocol packet, and to calculate an accuracy measure for the TX time-stamp, based on the assessed RX traffic pattern.

Abstract: An apparatus reads a chip design comprising first and second blocks corresponding to first and second hardware modules, nodes, and data path segments that each connect a pair of nodes or a node to a block. Tracing backward along data paths that terminate at the second block, the apparatus identifies a secure cone. The secure cone comprises secure path segments of the data paths terminating at the second block and corresponding nodes. The apparatus identifies data paths originating at the first block and that are at least partially within the secure cone and determines whether any terminate outside the secure cone. When none of the data paths originating at the first block terminate outside the secure cone, the apparatus verifies the chip design. When a data path originating at the first block terminates outside the secure cone, the apparatus determines that the chip design has a potential leak.

Abstract: A network device includes a network interface, a host interface and processing circuitry. The network interface is configured to connect to a communication network. The host interface is configured to connect to a host including a host processor running a client process. The processing circuitry is configured to receive packets originating from a peer process, to identify, in at least some of the received packets, application level information that is exchanged between the client process and the peer process, and to initiate reporting of one or more of the received packets to the client process, based on the application level information.