Abstract: A network adapter includes a network interface controller and a processor. The network interface controller is to communicate over a peripheral bus with a host, and over a network with a remote storage device. The processor is to expose on the peripheral bus a peripheral-bus device that communicates with the host using a bus storage protocol, to receive first I/O transactions of the bus storage protocol from the host, via the exposed peripheral-bus device, and to complete the first I/O transactions in the remote storage device by (i) translating between the first I/O transactions and second I/O transactions of a network storage protocol, and (ii) executing the second I/O transactions in the remote storage device. For receiving and completing the first I/O transactions, the processor is to cause the network interface controller to transfer data directly between the remote storage device and a memory of the host using zero-copy.

Abstract: Apparatuses, systems, and methods are described that provide improved networking communication systems and associated adapters. An example networking communication adapter includes an adapter housing defining a first end and a second end opposite the first end. The first end is configured to engage an Octal Small Form Factor Pluggable (OSFP) connector, and the second end is configured to receive a Quad Small Form Factor Pluggable Double Density (QSFP-DD) transceiver therein. The networking communication adapter further includes an inner connector positioned within the adapter housing. In an operational configuration in which the first end engages the OSFP connector and the second end receives the QSFP-DD transceiver, the inner connector operably connects the QSFP-DD transceiver with the OSFP connector such that signals may pass therebetween.

Abstract: A vertical-cavity surface-emitting laser (VCSEL) is provided that includes a mesa structure disposed on a substrate. The mesa structure defines an emission axis of the VCSEL. The mesa structure includes a first reflector, a second reflector, and a cascaded active region structure disposed between the first reflector and the second reflector. The cascaded active region structure includes a plurality of cascaded active region layers disposed along the emission axis, where each of the cascade active region layers includes an active region having multi-quantum well and/or dots layers (MQLs), a tunnel junction aligned with the emission axis, and an oxide confinement layer. The oxide confinement layer is disposed between the tunnel junction and MQLs, and has an electrical current aperture defined therein. The mesa structure defines an optical window through which the VCSEL is configured to emit light.

Abstract: A VCSEL includes an active region between a top distributed Bragg reflector (DBR) and a bottom DBR each having alternating GaAs and AlGaAs layers. The active region includes quantum wells (QW) confined between top and bottom GaAs-containing current-spreading layers (CSL), an aperture layer having an optical aperture and a tunnel junction layer above the QW. A GaAs intermediate layer configured to have an open top air gap is disposed over a boundary layer of the active region and the top DBR. The air gap is made wider than the optical aperture and has a height equal to one quarter of VCSEL's emission wavelength in air. The top DBR is attached to the intermediate layer by applying wafer bonding techniques. VCSEL output, the air gap, and the optical aperture are aligned on the same optical axis. The bottom DBR is epitaxially grown on a silicon or a GaAs substrate.

Abstract: A system comprises a first mechanism configured to hold a first block including a plurality of lenses located on or near a first surface of the first block. The plurality of lenses are configured to receive light to generate a plurality of light spots at or near a second surface of the first block opposite the first surface. The system includes a second mechanism configured to hold a second block including a plurality of waveguides, and to move the second block to bring the plurality of waveguides in alignment with the plurality of lenses using the plurality of light spots as alignment marks.

Abstract: A power distribution unit (PDU) comprises a housing, an input on the housing, and an input connector coupled to the input on the housing. The input connector is connectable to a power source that provides power for distribution by the PDU to one or more power consuming devices. The PDU includes an output including output connectors that provide blind-mate connection with a connection interface coupled to the one or more power consuming devices.

Abstract: In one embodiment, a secure computing system comprises a key generation sub-system configured to generate cryptographic keys and corresponding key labels for distribution to computer clusters, each computer cluster including a plurality of respective endpoints, a plurality of quantum key distribution (QKD) devices connected via respective optical fiber connections, and configured to securely distribute the generated cryptographic keys among the computer clusters, and a key orchestration sub-system configured to manage caching of the cryptographic keys in advance of receiving key requests from applications running on ones of the endpoints, and provide respective ones of the cryptographic keys to the applications to enable secure communication among the applications.

Abstract: Switches for performing packet switching and associated methods are provided. An example switch includes an ingress port for receiving a packet. The switch includes a plurality of egress ports for discharging the packet from the switch. The switch includes a plurality of egress queues with each egress queue associated with one of the plurality of egress ports. The switch includes a control plane configured to determine a descriptor associated with a packet, determine a first egress port from which to discharge the at least one packet and to transmit the descriptor to an egress queue associated with the first egress port. The switch includes a descriptor crossbar configured to transmit the descriptor from the egress queue to a second egress port of the plurality of egress ports. The switch includes a packet crossbar configured to transmit the at least one packet from the ingress port to the second egress port.

Abstract: A network device includes processing circuitry and multiple ports. The multiple ports are configured to connect to a communication network. The processing circuitry is configured to select a first port among the multiple ports to serve as an egress port for a packet, and to forward the packet to the first port, irrespective of whether or not the first port is usable as the egress port. The processing circuitry is further configured to, when the first port is usable as the egress port, transmit the packet to the communication network via the first port, and when the first port is unusable as the egress port, forward the packet from the first port to a second port among the multiple ports and transmit the packet to the communication network via the second port.

Abstract: In one embodiment, a network device, including packet processing circuitry, which includes at least one interface configured to receive packets, and packet forwarding circuitry configured to make respective forwarding decisions for respective ones of the packets, wherein the packet processing circuitry is configured to assign sequence numbers to the packets in at least one stage of packet processing, find missing packets in at least one corresponding later stage of the packet processing responsively to checking for missing sequence numbers among the assigned sequence numbers, and report the missing packets.

Abstract: A network device includes a port, a transmission pipeline and a time-stamping circuit. The port is configured for connecting to a network. The transmission pipeline includes multiple pipeline stages and is configured to process packets and to send the packets to the network via the port. The time-stamping circuit is configured to temporarily suspend at least some processing of at least a given packet in the transmission pipeline, to verify whether a pipeline stage having a variable processing delay, located downstream from the time-stamping circuit, meets an emptiness condition, and, only when the pipeline stage meets the emptiness condition, to time-stamp the given packet and resume the processing of the given packet.

Abstract: An optical cable includes a single optical connector configured for insertion into an optical receptacle so as to receive optical signals at a plurality of different wavelengths from the optical receptacle, and multiple electrical connectors, configured for insertion into respective electrical receptacles. Each electrical connector includes a transceiver configured to convert the optical signals into electrical output signals for output to an electrical receptacle. The optical cable further includes a plurality of optical fibers, having respective first ends connected together to the single optical connector so as to receive the optical signals. Each of the optical fibers has a respective second end coupled to a respective one of the electrical connectors. Wavelength selection optics are associated with the optical fibers so that the transceiver in each of the electrical connectors receives the optical signals at a different, respective one of the wavelengths.

Abstract: A transceiver comprises a transmitter including a light source, a modulator coupled to the light source, a driver that drives the modulator according to a set of driving conditions to cause the modulator to output optical signals based on light from the light source, and an output that passes first portions of the optical signals output by the modulator. The transceiver further comprises a first detector that detects second portions of the optical signals output from the modulator, and a receiver including a second detector that detects optical signals from an external transmitter.

Abstract: A parsing apparatus includes a packet-type identification circuit and a parser. The packet-type identification circuit is to receive a packet to be parsed, and to identify a packet type of the packet by extracting a packet-type identifier from a defined field in the packet. The parser is to store one or more parsing templates that specify parsing of one or more respective packet types. When the packet type of the packet corresponds to a parsing template among the stored parsing templates, the parser is to parse the packet in accordance with the stored parsing template. When the packet type of the packet does not correspond to any of the stored parsing templates, the parser is to parse the packet using an alternative parsing scheme.

Abstract: In one embodiment, a system includes a first data communication device including packet processing circuitry to provide a probe packet including an egress timestamp TS1 indicating a time at which the probe packet egresses the first data communication device, and a network interface to send the probe packet via at least one network connection to a second data communication device, and receive from the second data communication device a response packet including the egress timestamp TS1, wherein the packet processing circuitry is configured to associate with the response packet an ingress timestamp TS2 indicating a time at which the response packet ingresses the first data communication device, and a network metric processor to compute a data latency in the at least one network connection responsively to TS1, TS2, and an indication of an internal latency of the probe packet in the second data communication device.

Abstract: In one embodiment, a synchronized communication system includes a plurality of compute nodes, and clock connections to connect the compute nodes in a closed loop configuration, wherein the compute nodes are configured to distribute among the compute nodes a master clock frequency from any selected one of the compute nodes.

Abstract: An electronic device includes a substrate having contact pads disposed thereon and traces interconnecting the contact pads. A first integrated circuit (IC) die is mounted on the substrate and includes a predefined set of circuit components arranged on the first IC die in a first geometrical pattern, which is non-symmetrical under reflection about a given axis in a plane of the die. A second IC die is mounted on the substrate and includes the predefined set of circuit components arranged on the second IC die in a second geometrical pattern, which is a mirror image of the first geometrical pattern with respect to the given axis.

Abstract: A computerized system for efficient interaction between a host, the host having a first operating system, and a second operating system, the system comprising a subsystem on the second operating system which extracts data, directly from a buffer which is local to the host, wherein the system is operative for mapping memory from one bus associated with the first operating system to a different bus, associated with the second operating system and from which different bus the memory is accessed, thereby to emulate a connection between the first and second operating systems by cross-bus memory mapping.

Abstract: Embodiments are disclosed for providing a silicon photonics collimator for wafer level assembly. An example apparatus includes a silicon photonics (SiP) device and a micro-optical passive element. The SiP device comprises a set of optical waveguides. The micro-optical passive element is mounted on an edge of a cavity etched into a silicon surface of the SiP device. Furthermore, the micro-optical passive element is configured to direct optical signals between the set of optical waveguides and an external optical element.

Abstract: Systems and method are provided. An illustrative system includes a first compute node having a first processing unit, a first compute node port, and a first peripheral component interconnect bus configured to carry data between the first processing unit and the first compute node port. The system may further include a multi-host network interface controller having a first multi-host port, where the first multi-host port is configured to connect with the first compute node port via a first peripheral component interconnect cable, a network port, where the network port is configured to receive a network interface of a networking cable, and processing circuitry configured to translate and carry data between the first multi-host port and the network port.