Abstract: A network device includes one or more ports for connecting to a communication network, packet processing circuitry and clock circuitry. The packet processing circuitry is configured to communicate packets over the communication network via the ports. The clock circuitry includes a hardware clock configured to indicate a network time used for synchronizing network devices in the communication network, and a built-in accuracy test circuit configured to check an accuracy of the hardware clock.

Abstract: Methods for fabricating vertical cavity surface emitting lasers (VCSELs) on a large wafer are provided. An un-patterned epi layer form is bonded onto a first reflector form. The first reflector form includes a first reflector layer and a wafer of a first substrate type. The un-patterned epi layer form includes a plurality of un-patterned layers on a wafer of a second substrate type. The first and second substrate types have different thermal expansion coefficients. A resulting bonded blank is substantially non-varying in a plane that is normal to an intended emission direction of the VCSEL. A first regrowth is performed to form first regrowth layers, some of which are patterned to form a tunnel junction pattern. A second regrowth is performed to form second regrowth layers. A second reflector form is bonded onto the second regrowth layers, wherein the second reflector form includes a second reflector layer.

Abstract: A polarization recovery device comprises an input that receives a first optical signal with unknown polarization and with at least one signal parameter at an initial value, a first output that outputs a second optical signal with known polarization and with the at least one signal parameter at or near the initial value, and a recovery block that generates the second optical signal based on the first optical signal.

Abstract: An apparatus includes a processor, configured to designate a memory region in a memory, and to issue (i) memory-access commands for accessing the memory and (ii) a conditional-fence command associated with the designated memory region. Memory-Access Control Circuitry (MACC) is configured, in response to identifying the conditional-fence command, to allow execution of the memory-access commands that access addresses within the designated memory region, and to defer the execution of the memory-access commands that access addresses outside the designated memory region, until completion of all the memory-access commands that were issued before the conditional-fence command.

Abstract: A system comprising a processing circuitry configured to: obtain a first ordered sequence of symbols associated with a corresponding second ordered sequence of transmitted symbols and including one or more errors, the errors being discrepancies between given symbols of the first ordered sequence and corresponding symbols of the second ordered sequence; determine, for each symbol of the first ordered sequence of symbols, an estimated transmitted symbol, utilizing a Decision Feedback Equalizer (DFE); and determine if the estimated transmitted symbol of a given symbol of the first ordered sequence of symbols, satisfies a saturation threshold condition; and determine an error hypothesis identifying one or more of the errors by comparing the estimated transmitted symbol of at least one symbol of the first ordered sequence of symbols with one or more pairs of thresholds.

Abstract: An OSFP optical transceiver having split multiple fiber optical port using reduced amount of MPO terminations is provided that includes two adjacent sockets integrated into the optical port of the OSFP optical transceiver. The two adjacent sockets are vertically oriented with respect to the mounting baseplate of the OSFP optical transceiver, and each of the two adjacent sockets is adapted to receive an MPO receptacle that terminates the proximal end of a bundle of fibers. The OSFP optical transceiver also includes an optical connection between each socket and a corresponding lens in the OSFP optical transceiver, for transmitting optical signals received from other transceivers into the OSFP optical transceiver and optical signals generated in the OSFP optical transceiver to other transceivers.

Abstract: A computing system including network elements arranged in at least one group. A plurality of the network elements are designated as spines and another plurality are designated as leaves, the spines and leaves are interconnected in a bipartite topology, and at least some of the spines and leaves are configured to: receive in a first leaf, from a source node, packets destined to a destination node via a second leaf, forward the packets via a first link to a first spine and to the second leaf via a second link, in response to detecting that the second link has failed, apply a detour path from the first leaf to the second leaf, including a detour link in a spine-to-leaf direction and another detour link a leaf-to-spine direction, and forward subsequent packets, which are received in the first leaf and are destined to the second leaf, via the detour path.

Abstract: A fast optical switch and networks comprising fast optical switches are disclosed herein. In an example embodiment, a fast optical switch includes two or more fabric switches; a first selector switch; and a second selector switch. The first selector switch may selectively pass a signal to one of the two or more fabric switches. The one of the two or more fabric switches may act on the received signal to provide a switched signal and the second selector switch may selectively receive the switched signal provided by the one of the two or more fabric switches. A slot of the fast optical switch comprises a transmission window of one of the two or more fabric switches that occurs in parallel with at least a portion of a reconfiguration window of the other of the two or more fabric switches.

Abstract: Apparatus including a network switch which includes switching circuitry to switch packets, packet drop decision circuitry to identify a packet that is to be dropped, packet duplication circuitry to duplicate the packet that is to be dropped, producing a first packet and a second packet, and packet exporting circuitry to export the first packet to a memory external to the switch via direct memory access (DMA). Related apparatus and methods are also provided.

Abstract: A network device includes an enclosure, a multi-chip module (MCM), an optical-to-optical connector, and a multi-core fiber (MCF) interconnect. The enclosure has a panel. The MCM is inside the enclosure. The optical-to-optical connector, which is mounted on the panel of the enclosure, is configured to transfer a plurality of optical communication signals. The MCF interconnect has a first end coupled to the MCM and a second end connected to the optical-to-optical connector on the panel, for routing the plurality of optical communication signals between the MCM and the panel.

Abstract: Example vertical cavity surface emitting lasers (VCSELs) include a mesa structure disposed on a substrate, the mesa structure including a first reflector, a second reflector defining at least one diameter, and an active cavity material structure disposed between the first and second reflectors; and a second contact layer disposed at least in part on top of the mesa structure and defining a physical emission aperture having a physical emission aperture diameter. The ratio of the physical emission aperture diameter to the at least one diameter is greater than or approximately 0.172 and/or the ratio of the physical emission aperture diameter to the at least one diameter is less than or approximately 0.36. An example VCSEL includes a substrate; a buffer layer disposed on a portion of the substrate; and an emission structure disposed on the buffer layer.

Abstract: A network device includes a network interface, a host interface and processing circuitry. The network interface is configured to connect to a communication network. The host interface is configured to connect to a host including a processor. The processing circuitry is configured to receive from the processor, via the host interface, a notification specifying an operation for execution by the network device, the operation including (i) multiple tasks that are executable by the network device, and (ii) execution dependencies among the tasks in response to the notification, the processing circuitry is configured to determine a schedule for executing the tasks, the schedule complying with the execution dependencies, and to execute the operation by executing the tasks of the operation is accordance with the schedule.

Abstract: In one embodiment, data communication apparatus includes a network interface for connection to a network and configured to receive a sequence of data packets from a remote device over the network, the sequence including data blocks, ones of the data blocks having block boundaries that are not aligned with payload boundaries of the packets, and packet processing circuitry to cryptographically process the data blocks using a block cipher so as to write corresponding cryptographically processed data blocks to a memory, while holding segments of respective ones of the received data blocks in the memory, such that the packet processing circuitry stores a first segment of a data block of a first packet in the memory until a second packet is received, and then cryptographically processes the first and second segments together so as to write a corresponding cryptographically processed data block to the memory.

Abstract: In one embodiment, a network flow sampling system includes packet processing circuitry to process data packets of multiple network flows, and an adaptive policer to, for each one network flow of the multiple network flows compute a quantity of flow-specific sampling credits to be assigned to the one network flow responsively to a quantity of the network flows currently being processed by the packet processing circuitry, assign the flow-specific sampling credits to the one network flow, sample at least one of the data packets of the one network flow responsively to availability of the flow-specific sampling credits of the one network flow yielding sampled data, while applying sampling fairness among the network flows, and remove at least one of the flow-specific sampling credits of the one network flow from availability responsively to sampling the at least one data packet of the one network flow.

Abstract: A network device includes processing circuitry and a plurality of ports. The ports connect to a communication network. The processing circuitry is configured to receive, via an input port, data packets and probe packets that are addressed to a common output port, to store the data packets in a first queue and the probe packets in a second queue, both the first queue and the second queue are served by the output port, to produce telemetry data indicative of a state of the network device, based on a processing path that the data packets traverse within the network device, to schedule transmission of the data packets from the first queue at a first priority, and schedule transmission of the probe packets from the second queue at a second priority higher than the first priority, and to modify the scheduled probe packets so as to carry the telemetry data.

Abstract: A network device includes multiple ports, multiple buffer slices, a controller, and buffer control circuitry. The multiple ports are configured to communicate packets over a network. The multiple buffer slices are linked respectively to the multiple ports. The controller is configured to allocate a group of two or more of the buffer slices to a selected port among the ports. The buffer control circuitry is configured to buffer the packets, communicated via the selected port, in the group of the buffer slices, using zero-copy buffering.

Abstract: A network device includes packet processing circuitry and queue management circuitry. The packet processing circuitry is configured to transmit and receive packets to and from a network. The queue management circuitry is configured to store, in a memory, a queue for queuing data relating to processing of the packets, the queue including a primary buffer and an overflow buffer, to choose between a normal mode and an overflow mode based on a defined condition, to queue the data only in the primary buffer when operating in the normal mode, and, when operating in the overflow mode, to queue the data in a concatenation of the primary buffer and the overflow buffer.

Abstract: A network element includes processing circuitry and multiple ports. The ports connect using links to a communication network. The processing circuitry is configured to receive packets via the ports and forward the received packets to respective destination addresses via the ports. The destination addresses are organized in address groups, each address group including multiple destination addresses of nodes connected to a common network element in the communication network. The processing circuitry is further configured to, in response to identifying that a given port connects to a faulty link, determine one or more address groups that became unreachable via the given port due to the faulty link, generate a notification reporting one or more of the determined address groups that are unreachable via any port other than the given port, and transmit the notification to one or more other network elements, via one or more ports other than the given port.

Abstract: In one embodiment, a network device, includes a network interface port configured to receive data symbols from a network node over a packet data network, at least some of the symbols being included in data packets, and controller circuitry including physical layer (PHY) circuitry, which includes receive PHY pipeline circuitry configured to process the received data symbols, and a counter configured to maintain a counter value indicative of a number of the data symbols in the receive PHY pipeline circuitry.

Abstract: A system includes a memory, including a plurality of memory locations having different respective addresses, and a processor. The processor is configured to compute one of the addresses from (i) a first sequence of bits derived from a tag of a data item, and (ii) a second sequence of bits representing a class of the data item. The processor is further configured to write the data item to the memory location having the computed address and/or read the data item from the memory location having the computed address. Other embodiments are also described.