Patents Assigned to MEMC
  • METHODS TO SLICE A SILICON INGOT
    Publication number: 20120024761
    Abstract: The present disclosure generally relates to methods for recovering silicon from saw kerf, or an exhausted abrasive slurry, resulting from the cutting of a silicon ingot, such as a single crystal or polycrystalline silicon ingot. More particularly, the present disclosure relates to methods for isolating and purifying silicon from saw kerf or the exhausted slurry, such that the resulting silicon may be used as a raw material, such as a solar grade silicon raw material.
    Type: Application
    Filed: October 13, 2011
    Publication date: February 2, 2012
    Applicant: MEMC ELECTRONIC MATERIALS, INC.
    Inventors: Alexis Grabbe, Tracy M. Ragan
  • Grinding Tool For Trapezoid Grinding Of A Wafer
    Publication number: 20120028555
    Abstract: A grinding tool for trapezoid grinding of a wafer on a profiling machine includes an annular wheel including a central hole adapted for mounting the wheel on a spindle. The wheel includes at least two grooves disposed at an outer edge of the wheel and the grooves are sized for receiving an outer edge of the wafer. At least one of the grooves is adapted for rough grinding of the wafer. At least one other of the grooves is adapted for fine grinding of the wafer.
    Type: Application
    Filed: July 30, 2010
    Publication date: February 2, 2012
    Applicant: MEMC ELECTRONIC MATERIALS, INC.
    Inventors: Guoqiang David Zhang, Roland Vandamme, Peter D. Albrecht
  • Semiconductor And Solar Wafers
    Publication number: 20120025353
    Abstract: A silicon-on-insulator or bonded wafer includes an upper portion having a trapezoid shape in cross-section and a lower portion having an outer peripheral edge having a curved shape.
    Type: Application
    Filed: July 30, 2010
    Publication date: February 2, 2012
    Applicant: MEMC ELECTRONIC MATERIALS, INC.
    Inventors: Guoqiang David Zhang, Roland Vandamme
  • Methods For In-Situ Passivation Of Silicon-On-Insulator Wafers
    Publication number: 20120003814
    Abstract: Methods and systems are disclosed for performing a passivation process on a silicon-on-insulator wafer in a chamber in which the wafer is cleaved. A bonded wafer pair is cleaved within the chamber to form the silicon-on-insulator (SOI) wafer. A cleaved surface of the SOI wafer is then passivated in-situ by exposing the cleaved surface to a passivating substance. This exposure to a passivating substance results in the formation of a thin layer of oxide on the cleaved surface. The silicon-on-insulator wafer is then removed from the chamber. In other embodiments, the silicon-on-insulator wafer is first transferred to an adjoining chamber where the wafer is then passivated. The wafer is transferred to the adjoining chamber without exposing the wafer to the atmosphere outside the chambers.
    Type: Application
    Filed: June 16, 2011
    Publication date: January 5, 2012
    Applicant: MEMC ELECTRONIC MATERIALS, INC.
    Inventors: Michael J. Ries, Dale A. Witte, Anca Stefanescu, Andrew M. Jones
  • Methods for preparing a semiconductor wafer with high thermal conductivity
    Publication number: 20110318912
    Abstract: This invention generally relates to an epitaxial silicon semiconductor wafer with increased thermal conductivity to transfer heat away from a device layer, while also having resistance to common failure mechanisms, such as latch-up failures and radiation event failures. The semiconductor wafer comprises a lightly-doped device layer, a highly-doped protective layer, and a lightly-doped substrate. The invention is also directed to a process for forming such an epitaxial silicon wafer.
    Type: Application
    Filed: September 2, 2011
    Publication date: December 29, 2011
    Applicant: MEMC Electronic Materials, Inc.
    Inventor: Michael R. Seacrist
  • Methods for preparing a semiconductor structure for use in backside illumination applications
    Patent number: 8080482
    Abstract: This invention generally relates to an epitaxial silicon semiconductor wafer with increased thermal conductivity to transfer heat away from a device layer, while also having resistance to common failure mechanisms, such as latch-up failures and radiation event failures. The semiconductor wafer comprises a lightly-doped device layer, a highly-doped protective layer, and a lightly-doped substrate. The invention is also directed to a process for forming such an epitaxial silicon wafer.
    Type: Grant
    Filed: May 19, 2009
    Date of Patent: December 20, 2011
    Assignee: MEMC Electronic Materials, Inc.
    Inventor: Michael R. Seacrist
  • Methods for processing silicon on insulator wafers
    Patent number: 8080464
    Abstract: Methods are provided for etching and/or depositing an epitaxial layer on a silicon-on-insulator structure comprising a handle wafer, a silicon layer, and a dielectric layer between the handle wafer and the silicon layer. The silicon layer has a cleaved surface defining an outer surface of the structure. The cleaved surface of wafer is then etched while controlling a temperature of the reactor such that the etching reaction is kinetically limited. An epitaxial layer is then deposited on the wafer while controlling the temperature of the reactor such that a rate of deposition on the cleaved surface is kinetically limited.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: December 20, 2011
    Assignee: MEMC Electronics Materials, Inc,
    Inventors: Swapnil Y. Dhumal, Lawrence P. Flannery, Thomas A. Torack, John A. Pitney
  • Trichlorosilane Vaporization System
    Publication number: 20110300050
    Abstract: A heat exchanger for vaporizing a liquid and a method of using the same are disclosed herein. The heat exchanger includes a housing, a tube, a heater, and a plurality of non-reactive members. The tube is disposed in the interior of the housing and has an inlet and an outlet. The heater is configured to heat the tube. The plurality of non-reactive members are disposed in an interior cavity of the tube in an arrangement such that a plurality of voids are defined between the members and the tube. The arrangement also permits liquid to pass through the voids and travel from the inlet of the tube to the outlet of tube. The plurality of non-reactive members and the tube transfer heat to the liquid as the liquid passes through the plurality of voids in order to vaporize the liquid.
    Type: Application
    Filed: June 8, 2010
    Publication date: December 8, 2011
    Applicant: MEMC ELECTRONIC MATERIALS, INC.
    Inventors: Abarajith Hari, Zhihui Gu, Satish Bhusarapu, Timothy Truong, Puneet Gupta
  • Angle Of Repose Valve
    Publication number: 20110297861
    Abstract: An angle of repose valve for controlling the flow of granules and a method of repairing a leak in an angle of repose valve are disclosed herein. The angle of repose valve has a housing with an interior cavity, an inlet, and an outlet. A gas is used to convey granules through the valve and the housing has a thickness such that the gas can have a pressure of at least 70 psi. A saddle is disposed in the interior cavity of the housing and is coupled to a rotatable shaft that passes through an opening in the housing. A chevron seal is disposed between the shaft and a sealing member. A compression member is threadably engaged with the sealing member and is operable to exert force on the chevron seal to expand the chevron seal against the shaft and/or the housing to prevent and/or repair leaks of gas therethrough.
    Type: Application
    Filed: June 8, 2010
    Publication date: December 8, 2011
    Applicant: MEMC ELECTRONIC MATERIALS, INC.
    Inventors: Robert Cronin, Robert Cook, Lee Ferry, Satish Bhusarapu
  • Wafer clamping device for a double side grinder
    Patent number: 8066553
    Abstract: A hydrostatic pad for use in holding a semiconductor wafer during grinding of the wafer by grinding wheels. The pad includes hydrostatic pockets formed in a face of the body directly opposed to the wafer. The pockets are adapted for receiving fluid through the body and into the pockets to provide a barrier between the body face and the workpiece while still applying pressure to hold the workpiece during grinding. The hydrostatic pads allow the wafer to rotate relative to the pads about their common axis. The pockets are oriented to reduce hydrostatic bending moments that are produced in the wafer when the grinding wheels shift or tilt relative to the hydrostatic pads, helping prevent nanotopology degradation of surfaces of the wafer commonly caused by shift and tilt of the grinding wheels.
    Type: Grant
    Filed: January 20, 2005
    Date of Patent: November 29, 2011
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Milind S. Bhagavat, Puneet Gupta, Roland Vandamme, Takuto Kazama, Noriyuki Tachi
  • Methods for producing smooth wafers
    Patent number: 8058173
    Abstract: Methods for reducing the surface roughness of semiconductor wafers through a combination of rough polishing and thermally annealing the wafer.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: November 15, 2011
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Larry W. Shive, Brian L. Gilmore
  • Wafer Support Ring
    Publication number: 20110269316
    Abstract: A wafer support ring and a method of using the same are disclosed herein. The support ring supports a wafer during a first processing operation. A top surface of the support ring is in contact with a first plurality of locations on a surface of the wafer during the first processing operation. A second wafer support structure is used to support the wafer during a second processing operation. A top surface of the second wafer support structure is in contact with a second, different plurality of locations on the surface of the wafer during the second processing operation. The wafer support ring may also have an outer lip disposed about an outer periphery of the support ring that has a depth such that it does not form part of the top surface of the support ring.
    Type: Application
    Filed: May 3, 2010
    Publication date: November 3, 2011
    Applicant: MEMC ELECTRONIC MATERIALS, INC.
    Inventor: Brian Lawrence Gilmore
  • Low thermal mass semiconductor wafer support
    Patent number: 8042697
    Abstract: A support for a semiconductor wafer includes a plate having a support surface for supporting the wafer and a recessed surface spaced from the support surface and spaced from the wafer. A plurality of holes extends from the recessed surface, and the support surface is free of holes to inhibit contamination of the wafer.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: October 25, 2011
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Brian Lawrence Gilmore, Lance G. Hellwig
  • BELL JAR FOR SIEMENS REACTOR INCLUDING THERMAL RADIATION SHIELD
    Publication number: 20110250366
    Abstract: A bell jar for a Siemens reactor of the type used to deposit polycrystalline silicon on a plurality of heated silicon rods via chemical vapor deposition process. The bell jar includes a thermally conductive inner wall having an interior surface at least partially defining an interior space adapted to receive the plurality of heated silicon rods therein. A thermal radiation shield is in the interior space generally adjacent to and in opposing relationship with the interior surface of the inner wall. The thermal radiation shield is substantially opaque to thermal radiation emitted from the plurality of heated silicon rods in the interior space of the bell jar.
    Type: Application
    Filed: April 11, 2011
    Publication date: October 13, 2011
    Applicant: MEMC ELECTRONIC MATERIALS, S.P.A.
    Inventors: Gianluca Pazzaglia, Matteo Fumagalli, Milind Kulkarni
  • EPITAXIAL WAFER HAVING A HEAVILY DOPED SUBSTRATE AND PROCESS FOR THE PREPARATION THEREOF
    Publication number: 20110250739
    Abstract: This invention generally relates to a process for suppressing silicon self-interstitial diffusion near the substrate/epitaxial layer interface of an epitaxial silicon wafer having a heavily doped silicon substrate and a lightly doped silicon epitaxial layer. Interstitial diffusion into the epitaxial layer is suppressed by a silicon self-interstitial sink layer comprising dislocation loops.
    Type: Application
    Filed: June 21, 2011
    Publication date: October 13, 2011
    Applicant: MEMC ELECTRONIC MATERIALS, INC.
    Inventors: Robert J. Falster, Vladimir V. Voronkov, Luca Moiraghi, DongMyun Lee, Chanrae Cho, Marco Ravani
  • METHODS FOR PRODUCING POLYCRYSTALLINE SILICON THAT REDUCE THE DEPOSITION OF SILICON ON REACTOR WALLS
    Publication number: 20110244124
    Abstract: Gas distribution units of fluidized bed reactors are configured to direct thermally decomposable compounds to the center portion of the reactor and away from the reactor wall to prevent deposition of material on the reactor wall and process for producing polycrystalline silicon product in a reactor that reduce the amount of silicon which deposits on the reactor wall.
    Type: Application
    Filed: June 17, 2011
    Publication date: October 6, 2011
    Applicant: MEMC ELECTRONIC MATERIALS, INC.
    Inventors: Milind S. Kulkarni, Puneet Gupta, Balaji Devulapalli, Jameel Ibrahim, Vithal Revankar, Kwasi Foli
  • Hydrostatic Pad Pressure Modulation in a Simultaneous Double Side Wafer Grinder
    Publication number: 20110237160
    Abstract: Systems and methods are disclosed for modulating the hydrostatic pressure in a double side wafer grinder having a pair of grinding wheels. The systems and methods use a processor to measure the amount of electrical current drawn by the grinding wheels. Pattern detection software is used to predict a grinding stage based on the measured electrical current. The hydrostatic pressure is changed by flow control valves at each stage to change the clamping pressure applied to the wafer and to thereby improve nanotopology in the processed wafer.
    Type: Application
    Filed: March 16, 2011
    Publication date: September 29, 2011
    Applicant: MEMC ELECTRONIC MATERIALS, INC.
    Inventors: Sumeet S. Bhagavat, Roland R. Vandamme, Tomomi Komura
  • Arsenic and phosphorus doped silicon wafer substrates having intrinsic gettering
    Patent number: 8026145
    Abstract: A process for the preparation of low resistivity arsenic or phosphorous doped (N+/N++) silicon wafers which, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, reliably form oxygen precipitates.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: September 27, 2011
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Robert J. Falster, Vladimir Voronkov, Gabriella Borionetti
  • METHOD AND SYSTEM FOR STRIPPING THE EDGE OF A SEMICONDUCTOR WAFER
    Publication number: 20110223741
    Abstract: A method and a system are described herein for applying etchant to edges of a plurality of wafers. The system includes a sump configured for holding etchant, a roller having an outer surface in fluid communication with the sump and configured to have etchant thereon, a wafer cassette configured to retain wafers positioned therein so that edges of the wafers are in contact with the roller. The cassette permits axial rotation of the wafers about an axis. A method of applying etchant to the edge of the wafer includes placing the wafer edge in contact with the roller and rotating the roller about a longitudinal axis of the roller. At least a portion of the roller contact an etchant contained in a sump during rotation so that etchant is applied to the wafer edge.
    Type: Application
    Filed: November 16, 2009
    Publication date: September 15, 2011
    Applicant: MEMC ELECTRONIC MATERIALS, INC.
    Inventor: Robert W. Standley
  • METHODS FOR MONITORING THE AMOUNT OF METAL CONTAMINATION IMPARTED INTO WAFERS DURING A SEMICONDUCTOR PROCESS
    Publication number: 20110212547
    Abstract: Methods are disclosed for monitoring the amount of metal contamination imparted during wafer processing operations such as polishing and cleaning. The methods include subjecting a silicon-on-insulator structure to the semiconductor process, precipitating metal contamination in the structure and delineating the metal contaminants.
    Type: Application
    Filed: May 11, 2011
    Publication date: September 1, 2011
    Applicant: MEMC ELECTRONIC MATERIALS, INC.
    Inventors: Jeffrey L. Libbert, Lu Fei