Patents Assigned to MEMC
  • METHODS FOR MONITORING THE AMOUNT OF METAL CONTAMINATION IMPARTED INTO WAFERS DURING A SEMICONDUCTOR PROCESS
    Publication number: 20110212547
    Abstract: Methods are disclosed for monitoring the amount of metal contamination imparted during wafer processing operations such as polishing and cleaning. The methods include subjecting a silicon-on-insulator structure to the semiconductor process, precipitating metal contamination in the structure and delineating the metal contaminants.
    Type: Application
    Filed: May 11, 2011
    Publication date: September 1, 2011
    Applicant: MEMC ELECTRONIC MATERIALS, INC.
    Inventors: Jeffrey L. Libbert, Lu Fei
  • METHODS FOR REDUCING THE WIDTH OF THE UNBONDED REGION IN SOI STRUCTURES
    Publication number: 20110207246
    Abstract: The disclosure relates to preparation of silicon on insulator structures with reduced unbonded regions and to methods for producing such wafers by minimizing the roll-off amount (ROA) of the handle and donor wafers. Methods for polishing wafers are also provided.
    Type: Application
    Filed: February 4, 2011
    Publication date: August 25, 2011
    Applicant: MEMC ELECTRONIC MATERIALS, INC.
    Inventors: John A. Pitney, Ichiro Yoshimura, Lu Fei
  • SEMICONDUCTOR WAFERS WITH REDUCED ROLL-OFF AND BONDED AND UNBONDED SOI STRUCTURES PRODUCED FROM SAME
    Publication number: 20110204471
    Abstract: The disclosure relates to preparation of silicon on insulator structures with reduced unbonded regions and to methods for producing such wafers by minimizing the roll-off amount (ROA) of the handle and donor wafers. Methods for polishing wafers are also provided.
    Type: Application
    Filed: February 4, 2011
    Publication date: August 25, 2011
    Applicant: MEMC ELECTRONIC MATERIALS, INC.
    Inventors: John A. Pitney, Ichiro Yoshimura, Lu Fei
  • Crucible For Use In A Directional Solidification Furnace
    Publication number: 20110180229
    Abstract: A directional solidification furnace comprises a crucible assembly including a crucible for containing a melt having walls and a base with an opening therein, a crucible support for supporting the crucible, and a lid covering the crucible. A plate is received in the opening in the base. The plate has a higher thermal conductivity than that of the base. The base can include a composite having an additive such that the composite base has a higher thermal conductivity than a comparable without the additive.
    Type: Application
    Filed: January 27, 2011
    Publication date: July 28, 2011
    Applicant: MEMC SINGAPORE PTE. LTD. (UEN200614794D)
    Inventors: Richard J. Phillips, Balaji Devulapalli, Steven L. Kimbel, Aditya J. Deshpande
  • SUPPRESSION OF OXYGEN PRECIPITATION IN HEAVILY DOPED SINGLE CRYSTAL SILICON SUBSTRATES
    Publication number: 20110177682
    Abstract: This invention generally relates to a process for suppressing oxygen precipitation in epitaxial silicon wafers having a heavily doped silicon substrate and a lightly N-doped silicon epitaxial layer by dissolving existing oxygen clusters and precipitates within the substrate. Furthermore, the formation of oxygen precipitates is prevented upon subsequent oxygen precipitation heat treatment.
    Type: Application
    Filed: February 4, 2011
    Publication date: July 21, 2011
    Applicant: MEMC ELECTRONIC MATERIALS, INC.
    Inventors: Robert J. Falster, Luca Moiraghi, DongMyun Lee, Chanrae Cho, Marco Ravani
  • SILICON WAFERS AND INGOTS WITH REDUCED OXYGEN CONTENT AND METHODS FOR PRODUCING THEM
    Publication number: 20110177284
    Abstract: Silicon nitride coated crucibles for holding melted semiconductor material and for use in preparing multicrystalline silicon ingots by a directional solidification process; methods for coating crucibles; methods for preparing silicon ingots and wafers; compositions for coating crucibles and silicon ingots and wafers with a low oxygen content.
    Type: Application
    Filed: July 16, 2010
    Publication date: July 21, 2011
    Applicant: MEMC SINGAPORE PTE LTD.
    Inventors: Richard J. Phillips, Steven L. Kimbel, Aditya J. Deshpande, Gang Shi
  • BULK SILICON WAFER PRODUCT USEFUL IN THE MANUFACTURE OF THREE DIMENSIONAL MULTIGATE MOSFETS
    Publication number: 20110163313
    Abstract: A method for preparing a semiconductor structure for use in the manufacture of three dimensional transistors, the structure comprising a silicon substrate and an epitaxial layer, the epitaxial layer comprising an endpoint detection epitaxial region comprising an endpoint detection impurity selected from the group consisting of carbon, germanium, or a combination.
    Type: Application
    Filed: August 20, 2009
    Publication date: July 7, 2011
    Applicant: MEMC ELECTRONIC MATERIALS, INC.
    Inventor: Michael R. Seacrist
  • METHODS FOR REDUCING THE DEPOSITION OF SILICON ON REACTOR WALLS USING PERIPHERAL SILICON TETRACHLORIDE
    Publication number: 20110158888
    Abstract: Fluidized bed reactor systems and distributors are disclosed as well as processes for producing polycrystalline silicon from a thermally decomposable silicon compound such as trichlorosilane. The processes generally involve reduction of silicon deposits on reactor walls during polycrystalline silicon production by use of a silicon tetrahalide.
    Type: Application
    Filed: December 23, 2010
    Publication date: June 30, 2011
    Applicant: MEMC ELECTRONIC MATERIALS, INC.
    Inventor: Henry F. Erk
  • Methods For Generating Representations of Flatness Defects on Wafers
    Publication number: 20110160890
    Abstract: Methods are disclosed for generating a representation of flatness defects on a wafer. Data is received describing the thickness of the wafer at a plurality of points on a wafer divided into a plurality of sites. A reference plane is defined for each of the plurality of sites. For each of the sites, an upper plane and a lower plane are defined relative to the reference plane. A determination is made as to which of the plurality of points on the wafer represents a flatness defect by identifying which points are not disposed between the upper plane and lower plane. A representation is then generated depicting a location of each of the flatness defects on the wafer. In some embodiments, a single representation is generated depicting the location of flatness defects on a plurality of wafers.
    Type: Application
    Filed: December 29, 2009
    Publication date: June 30, 2011
    Applicant: MEMC ELECTRONIC MATERIALS, INC.
    Inventor: John A. Pitney
  • METHOD FOR THE PREPARATION OF A MULTI-LAYERED CRYSTALLINE STRUCTURE
    Publication number: 20110159665
    Abstract: This invention generally relates to a process for making a multi-layered crystalline structure. The process includes implanting ions into a donor structure, bonding the implanted donor structure to a second structure to form a bonded structure, cleaving the bonded structure, and removing any residual portion of the donor structure from the finished multi-layered crystalline structure.
    Type: Application
    Filed: December 21, 2010
    Publication date: June 30, 2011
    Applicant: MEMC ELECTRONIC MATERIALS, INC.
    Inventors: Dale A. Witte, Jeffrey L. Libbert
  • Methods For Processing Silicon On Insulator Wafers
    Publication number: 20110159668
    Abstract: Methods are provided for etching and/or depositing an epitaxial layer on a silicon-on-insulator structure comprising a handle wafer, a silicon layer, and a dielectric layer between the handle wafer and the silicon layer. The silicon layer has a cleaved surface defining an outer surface of the structure. The cleaved surface of wafer is then etched while controlling a temperature of the reactor such that the etching reaction is kinetically limited. An epitaxial layer is then deposited on the wafer while controlling the temperature of the reactor such that a rate of deposition on the cleaved surface is kinetically limited.
    Type: Application
    Filed: December 17, 2010
    Publication date: June 30, 2011
    Applicant: MEMC ELECTRONIC MATERIALS, INC.
    Inventors: Swapnil Y. Dhumal, Lawrence P. Flannery, Thomas A. Torack, John A. Pitney
  • Methods For Producing Silicon Tetrafluoride
    Publication number: 20110158882
    Abstract: Methods for producing silicon tetrafluoride by acid digestion of fluoride salts of alkali metal or alkaline earth metal and aluminum, optionally, in the presence of a source of silicon; methods for producing silane that include acid digestion of by-products of silane production to produce silicon tetrafluoride.
    Type: Application
    Filed: December 15, 2010
    Publication date: June 30, 2011
    Applicant: MEMC ELECTRONIC MATERIALS, INC.
    Inventors: Satish Bhusarapu, Puneet Gupta
  • FLUIDIZED BED REACTOR SYSTEMS AND DISTRIBUTORS FOR USE IN SAME
    Publication number: 20110158857
    Abstract: Fluidized bed reactor systems and distributors are disclosed as well as processes for producing polycrystalline silicon from a thermally decomposable silicon compound such as trichlorosilane. The processes generally involve reduction of silicon deposits on reactor walls during polycrystalline silicon production by use of a silicon tetrahalide.
    Type: Application
    Filed: December 23, 2010
    Publication date: June 30, 2011
    Applicant: MEMC ELECTRONIC MATERIALS, INC.
    Inventor: Henry F. Erk
  • Methods For Producing Aluminum Trifluoride
    Publication number: 20110158896
    Abstract: Methods for producing aluminum trifluoride by acid digestion of fluoride salts of alkali metal or alkaline earth metal and aluminum, optionally, in the presence of a source of silicon; methods for producing silane that include acid digestion of by-products of silane production to produce aluminum trifluoride.
    Type: Application
    Filed: December 15, 2010
    Publication date: June 30, 2011
    Applicant: MEMC ELECTRONIC MATERIALS, INC.
    Inventors: Puneet Gupta, Satish Bhusarapu
  • Systems For Generating Representations of Flatness Defects on Wafers
    Publication number: 20110160891
    Abstract: Systems and computer-readable media having computer-executable components are disclosed for generating a representation of flatness defects on a wafer. Data is received describing the thickness of the wafer at a plurality of points on a wafer divided into a plurality of sites. A reference plane is defined for each of the plurality of sites. For each of the sites, an upper plane and a lower plane are defined relative to the reference plane. A determination is made as to which of the plurality of points on the wafer represents a flatness defect by identifying which points are not disposed between the upper plane and lower plane. A representation is then generated depicting a location of each of the flatness defects on the wafer. In some embodiments, a single representation is generated depicting the location of flatness defects on a plurality of wafers.
    Type: Application
    Filed: December 29, 2009
    Publication date: June 30, 2011
    Applicant: MEMC ELECTRONIC MATERIALS, INC.
    Inventor: John A. Pitney
  • METHODS FOR MONITORING THE AMOUNT OF CONTAMINATION IMPARTED INTO SEMICONDUCTOR WAFERS DURING WAFER PROCESSING
    Publication number: 20110151592
    Abstract: Methods are disclosed for monitoring the amount of metal contamination imparted during wafer processing operations such as polishing and cleaning. The methods include subjecting a silicon-on-insulator structure to the semiconductor process, precipitating metal contamination in the structure and delineating the metal contaminants.
    Type: Application
    Filed: December 16, 2010
    Publication date: June 23, 2011
    Applicant: MEMC ELECTRONIC MATERIALS, INC.
    Inventors: Jeffrey L. Libbert, Lu Fei
  • Semiconductor Wafer Transport System
    Publication number: 20110148128
    Abstract: A system and a wand are disclosed for the transport of a semiconductor wafer. The system and wand include a plate and a locator. The plate includes a plurality of plate outlets for directing gas flow against the wafer to hold the wafer using the Bernoulli principle. The locator extends from the plate and includes a locating outlet for directing a gas flow to locate the wafer laterally relative to the plate. The plate outlets and the locating outlet operate to prevent the wafer from contacting the plate or the locator. In some embodiments, a plurality of locators are used to locate the wafer laterally relative to the plate.
    Type: Application
    Filed: December 23, 2009
    Publication date: June 23, 2011
    Applicant: MEMC ELECTRONIC MATERIALS, INC.
    Inventors: Lance G. Hellwig, Thomas A. Torack, John A. Pitney
  • Systems And Methods For Analysis of Water and Substrates Rinsed in Water
    Publication number: 20110146717
    Abstract: A system and method are disclosed for predicting the amount of contaminants deposited on a substrate, such as a semiconductor wafer, after contact the wafer with water in a container. The contaminants may includes materials that negatively affect the properties of the wafer even when the amount of contaminants deposited on the surface of the wafer is below the threshold level of detection of known systems. The method includes contacting the wafer with water for a first period of time, the wafer having wafer surfaces, drying the wafer, analyzing the wafer to determine contaminants on the wafer surfaces, and predicting the amount of contaminants deposited on the wafer when contacting the wafer with water for a second period of time shorter than the first period of time.
    Type: Application
    Filed: December 14, 2010
    Publication date: June 23, 2011
    Applicant: MEMC ELECTRONIC MATERIALS, INC.
    Inventor: Larry W. Shive
  • Process and System for the Purification of Trichlorosilane and Silicon Tetrachloride
    Publication number: 20110114469
    Abstract: The present disclosure relates to processes and systems for purifying technical grade trichlorosilane and/or technical grade silicon tetrachloride into electronic grade trichlorosilane and/or electronic grade silicon tetrachloride.
    Type: Application
    Filed: January 26, 2011
    Publication date: May 19, 2011
    Applicant: MEMC ELECTRONIC MATERIALS, S.P.A.
    Inventor: Gianfranco Ghetti
  • Processes for purification of silicon tetrafluoride
    Patent number: 7943108
    Abstract: Processes for purifying silicon tetrafluoride source gas by subjecting the source gas to one or more purification processes including: contacting the silicon tetrafluoride source gas with an ion exchange resin to remove acidic contaminants, contacting the silicon tetrafluoride source gas with a catalyst to remove carbon monoxide, by removal of carbon dioxide by use of an absorption liquid, and by removal of inert compounds by cryogenic distillation; catalysts suitable for removal of carbon monoxide from silicon tetrafluoride source gas and processes for producing such catalysts.
    Type: Grant
    Filed: September 11, 2008
    Date of Patent: May 17, 2011
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Vithal Revankar, Jameel Ibrahim