Abstract: Methods for producing silane by reacting a hydride and a halosilane are disclosed. Some embodiments involve use of a column which is not mechanically agitated and in which reactants may be introduced in a counter-current arrangement. Some embodiments involve use of a baffled column which has multiple reaction zones.

Abstract: Systems and methods are provided for cleaning an interior surface of a chemical vapor deposition reactor bell used in the production of polysilicon.

Abstract: The invention concerns a process (and a corresponding plant) for the purification of trichlorosilane and/or silicon tetrachloride comprising the following steps of treating technical grade trichlorosilane and/or technical grade silicon tetrachloride: complexation of the boron impurities (trichloride (BCl3)) and other metallic impurities by addition of diphenylthiocarbazone and/or triphenylchloromethane, with the formation of complex macromolecules having high boiling point, first column distillation of the complexation step products, wherein the complexed boron impurities, together with other metallic impurities are removed as bottoms, and second column distillation of the tops of the previous distillation, wherein electronic grade trichlorosilane (plus dichlorosilane possible present); and/or silicon tetrachloride are obtained as tops and phosphorus chlorides (PCl3) and phosphorus containing compounds, arsenic chlorides (AsCl3) and arsenic containing compounds, aluminium compounds, antimony compounds and in

Abstract: Systems and computer-readable media having computer-executable components are disclosed for generating a representation of flatness defects on a wafer. Data is received describing the thickness of the wafer at a plurality of points on a wafer divided into a plurality of sites. A reference plane is defined for each of the plurality of sites. For each of the sites, an upper plane and a lower plane are defined relative to the reference plane. A determination is made as to which of the plurality of points on the wafer represents a flatness defect by identifying which points are not disposed between the upper plane and lower plane. A representation is then generated depicting a location of each of the flatness defects on the wafer. In some embodiments, a single representation is generated depicting the location of flatness defects on a plurality of wafers.

Abstract: Systems and methods are provided for controlling silicon rod temperature. In one example, a method of controlling a surface temperature of at least one silicon rod in a chemical vapor deposition (CVD) reactor during a CVD process is presented. The method includes determining an electrical resistance of the at least one silicon rod, comparing the resistance to a set point to determine a difference, and controlling a power supply to control a power output coupled to the at least one silicon rod to minimize an absolute value of the difference.

Abstract: The disclosure relates to preparation of silicon on insulator structures with reduced unbonded regions and to methods for producing such wafers by minimizing the roll-off amount (ROA) of the handle and donor wafers. Methods for polishing wafers are also provided.

Abstract: A directional solidification furnace includes a crucible for holding molten silicon and a lid covering the crucible and forming an enclosure over the molten silicon. The crucible also includes an inlet in the lid for introducing inert gas above the molten silicon to inhibit contamination of the molten silicon.

Abstract: A heat exchanger system for use in a directional solidification furnace is disclosed. The heat exchanger includes a plate having a flow path formed in the plate for directing a flow of coolant. The flow path has an inlet positioned adjacent an outlet. A wall separates the inlet and the outlet of the flow path. The heat exchanger includes a cover having an opening in fluid communication with the inlet and the outlet of the flow path. An inner conduit is connected to the inlet of the flow path and an outer conduit is connected to the outlet of the flow path.

Abstract: A crystal puller for melting silicon and forming a single crystal ingot and a feed tool for shielding a portion of the crystal puller during charging of the crystal puller are disclosed herein. The crystal puller includes a crucible for containing molten silicon. The feed tool includes a cylinder and a plate. The cylinder has an inner surface and an annular ledge formed in a portion of the inner surface. The cylinder has a diameter at the annular ledge that is less than a diameter of the cylinder at the inner surface. The plate is positioned on the annular ledge and includes a first section separate from a second section. The first section and the second section are operable to move laterally with respect to each other. The plate has a central opening formed in at least one of the first section and the second section.

Abstract: The present disclosure generally relates to the manufacture of silicon wafers, and more particularly to edge etching apparatus and methods for etching the edge of a silicon wafer.

Abstract: A silicon-on-insulator or bonded wafer includes an upper portion having a trapezoid shape in cross-section and a lower portion having an outer peripheral edge having a curved shape.

Abstract: Methods for reducing or even eliminating dislocations in Czochralski-grown silicon ingots are disclosed. Generally, the methods involve controlling the growth conditions of the neck prior to formation of the ingot body.

Abstract: Methods are disclosed for inhibiting heat transfer through lateral sidewalls of a support member positioned beneath a crucible in a directional solidification furnace. The methods include the use of insulation positioned adjacent the lateral sidewalls of the support member. The insulation inhibits heat transfer through the lateral sidewalls of the support member to ensure the one-dimensional transfer of heat from the melt through the support member.

Abstract: The present disclosure relates to processes and systems for purifying technical grade trichlorosilane and/or technical grade silicon tetrachloride into electronic grade trichlorosilane and/or electronic grade silicon tetrachloride.

Abstract: Systems and methods for the ultrasonic cleaving of bonded wafer pairs are described. The system includes a tank for containing a volume of liquid, a wafer boat having a recess formed therein for receiving the bonded wafer pair. The recess has a pair of opposing, spaced-apart sidewalls disposed at an angle from a vertical axis. An ultrasonic agitator is configured to ultrasonically agitate the volume of liquid. The ultrasonic agitation of the volume of liquid results in the cleaving of the bonded wafer pair.

Abstract: Silicon nitride coated crucibles for holding melted semiconductor material and for use in preparing multicrystalline silicon ingots by a directional solidification process; methods for coating crucibles; methods for preparing silicon ingots and wafers; compositions for coating crucibles and silicon ingots and wafers with a low oxygen content.

Abstract: Systems and methods are disclosed for inhibiting heat transfer through lateral sidewalls of a support member positioned beneath a crucible in a directional solidification furnace. The systems and methods include the use of insulation positioned adjacent the lateral sidewalls of the support member. The insulation inhibits heat transfer through the lateral sidewalls of the support member to ensure the one-dimensional transfer of heat from the melt through the support member.

Abstract: Silicon on insulator structures having a high resistivity region in the handle wafer of the silicon on insulator structure are disclosed. Methods for producing such silicon on insulator structures are also provided. Exemplary methods involve creating a non-uniform thermal donor profile and/or modifying the dopant profile of the handle wafer to create a new resistivity profile in the handle wafer. Methods may involve one or more SOI manufacturing steps or electronic device (e.g., RF device) manufacturing steps.

Abstract: A tool for harvesting polycrystalline silicon-coated rods from a chemical vapor deposition reactor includes a body including outer walls sized for enclosing the rods within the outer walls. Each outer wall includes a door for allowing access to at least one of the rods.

Abstract: Silicon on insulator structures having a high resistivity region in the handle wafer of the silicon on insulator structure are disclosed. Methods for producing such silicon on insulator structures are also provided. Exemplary methods involve creating a non-uniform thermal donor profile and/or modifying the dopant profile of the handle wafer to create a new resistivity profile in the handle wafer. Methods may involve one or more SOI manufacturing steps or electronic device (e.g., RF device) manufacturing steps.