Abstract: A semiconductor storage device includes first, second, and third wiring layers, each including a plurality of first wirings, fourth and fifth wiring layers, each including a plurality of second wirings, wherein the fourth wiring layer is between the first and second wiring layers and the fifth wiring layer is between the second and third wiring layers, memory cells formed at intersections of the first and second wirings of adjacent wiring layers, first and second contacts electrically connected to a first wiring of the first wiring layer and a first wiring of the second wiring layer, respectively, in the hook-up region, a sixth wiring layer including a first connection wiring electrically connected to the first contact and a second connection wiring electrically connected to the second contact and separated from the first connection wiring, and first and second drive circuits electrically connected to the first and second connection wirings, respectively.

Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell. The control unit controls write, read, and erase of the nonvolatile semiconductor memory device. The control unit changes the read level between a start of use of the nonvolatile semiconductor memory device and a timing after an elapse of a time.

Abstract: A magnetic storage device of an embodiment includes: a first magnetic part including a first portion and a second portion and extending in a first direction from the first portion to the second portion; a layered part which is stacked on the first magnetic part in a second direction intersecting with the first direction; a first electrode electrically connected with the first portion; and a second electrode electrically connected with the second portion. The layered part includes a first layer and a second layer which is disposed between the first layer and the first magnetic part, the second layer includes a metal oxide, and the first layer includes at least one selected from the group consisting of a metal nitride and a metal carbide.

Abstract: A memory system includes a nonvolatile memory configured to execute one of a plurality of read operations, including a first read operation and a second read operation, and a memory controller configured to issue a read command to the nonvolatile memory to cause the nonvolatile memory to execute one of the plurality of read operations. The memory controller is configured to receive a read request, estimate a reliability level of a result of a read operation to be executed by the nonvolatile memory to read data from a physical address specified in the read request, select one of the first and second read operations to be executed first in a read sequence corresponding to the read request by the nonvolatile memory based on the estimated reliability level, and instruct the nonvolatile memory to execute the selected read operation.

Abstract: A semiconductor device according to an embodiment includes two semiconductor pillars, a connection member connected between the two semiconductor pillars, and a contact connected to the connection member. There is not a conductive member disposed between the two semiconductor pillars.

Abstract: According to one embodiment, a memory system includes a semiconductor memory device and a controller. The device includes a plurality of memory cells capable of storing at least first to third data and a word line coupled to the plurality of memory cells. The first data is determined by a first read operation including a first read level. The second data is determined by a second read operation including a second read level. The third data is determined by a third read operation including a third read level. The controller controls the semiconductor memory device to perform a forth read operation including the first and second read levels in a search operation for first to third read voltages corresponding to the first to third read levels, respectively.

Abstract: According to the present embodiment, a nonvolatile semiconductor memory device includes a memory string group including k stacked memory strings, each of the memory strings including a plurality of nonvolatile memory cells connected in series, a selection transistor group including k selection transistors, each of the k selection transistors corresponding to each of the k memory strings respectively, the selection transistor group divided into n selection transistor sub-groups, each of the n selection transistor sub-groups including k/n selection transistors, n bit lines arranged in parallel to each of the k memory strings, and n bit line contacts arranged perpendicularly, each of the n bit line contacts connected to each of the n bit lines, respectively, each of the n bit line contacts connected to the k/n selection transistors belonging to the each of the n selection transistor sub-group respectively.

Abstract: A data storage device comprises a non-volatile semiconductor memory device and a solid-state drive controller communicatively coupled to the non-volatile semiconductor memory device, including a function level reset manager. The function level reset manager can receive a function level reset request from a host system, generate a function level reset bitmap based on the function level reset request, and broadcast the function level reset request to a command processing pipeline. The function level reset bitmap can indicate which functions are in a reset state. Further, the function level reset manager can determine which functions are in the reset state and instruct the command processing pipeline to cancel commands associated with the functions in the reset state.

Abstract: In an SSD including a host interface, controller, non-volatile memory coupled to the controller, and volatile memory, data is stored in non-volatile memory in clusters having a cluster start address and a cluster end address. A mapping table is maintained in volatile memory, which indicates by a trim signature deallocated clusters in non-volatile memory. The trim table is populated with deallocated ranges and an associated offset within the non-volatile memory. The controller receives from the host interface a sequence of commands including a deallocate command including at least one address range including a start address and an end address, or a start address and a length of the address range. The controller processes the deallocate command by selecting one or both of a write-to-non-volatile-memory action and a record-to-volatile-memory action. In cases of power failure, the mapping table is restored for deallocated ranges at specific offsets recorded in the trim table.

Abstract: In an alignment mark of an embodiment, a first pattern includes a first portion and a second portion, a second pattern includes a third portion and a fourth portion, the first portion and the third portion partially overlap each other, the second portion and the fourth portion partially overlap each other, a pitch length of each structural periods of the first portion and the third portion are equal within 1.2 times, a pitch length of each structural periods of the second portion and the fourth portion are equal within 1.2 times, a duty ratio of each of the first and third portions is 1:1, and a duty ratio of the second portion is D:2, and D is an integer of two or more, the duty ratio being a ratio between a light-shielding portion and a light-transmitting portion.

Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, controller, memory, wireless communication function section, and extension register. The controller controls the nonvolatile semiconductor memory device. The memory is serving as a work area of the controller. The wireless communication module has a wireless communication function. The extension register is provided in the memory. The controller processes a first command to read data from the extension register, and a second command to write data to the extension register. The extension register records, an information specifying the type of the wireless communication function in a specific page, and an address information indicating a region on the extension register to which the wireless communication function is assigned.

Abstract: According to one embodiment, a semiconductor memory includes: a first bit line; a first select transistor having a first terminal connected to the first bit line; a first memory cell connected to a second terminal of the first select transistor; a circuit connected to the first bit line and applying an erase voltage to be applied to the first memory cell to the bit line via the first terminal and the second terminal; and a diode connected to the first bit line and the first circuit.

Abstract: According to one embodiment, a semiconductor memory device includes: a first memory cell; a second memory cell; a first word line; a second word line; and a first bit line. The first memory cell faces the second memory cell. When reading data from the first memory cell, the semiconductor memory device is configured to perform the first operation in which a first voltage is applied to the first word line and a second voltage higher than the first voltage is applied to the second word line, and perform the second operation in which a third voltage higher than the first voltage and a fourth voltage different from the third voltage are applied to the first word line and a fifth voltage lower than the second to the fourth voltage is applied to the second word line.

Abstract: According to an embodiment, an electronic apparatus includes a printed circuit board including a plurality of devices that include a nonvolatile memory package and a controller package configured to control the nonvolatile memory package, and a housing accommodating the printed circuit board. The housing includes an opening on a surface constituting the housing. An encryption device among the plurality of devices is present in a first region. The first region is a region on the printed circuit board that is not irradiated with light emitted from a light source placed at the opening. The encryption device is a device used for an encryption process of data to be stored into the nonvolatile memory package.

Abstract: According to an embodiment, a semiconductor memory, on receiving a first command, applies a voltage within a first range and a voltage within a second range to a word line and reads a first bit from a memory cell, and, on receiving a second command, applies a voltage within a third range to the word line and reads a second bit from the memory cell. The controller issues the first command a plurality of times and changes the voltages to be applied to the word line within the first range and the second range in accordance with the plurality of first commands, specifies a first and second voltage within the first and the second range, respectively, and estimates a third voltage within the third range. The voltage applied to read the second bit is the estimated third voltage.

Abstract: According to one embodiment, a memory device includes a nonvolatile memory, address translation unit, generation unit, and reception unit. The nonvolatile memory includes erase unit areas. Each of the erase unit areas includes write unit areas. The address translation unit generates address translation information relating a logical address of write data written to the nonvolatile memory to a physical address indicative of a write position of the write data in the nonvolatile memory. The generation unit generates valid/invalid information indicating whether data written to the erase unit areas is valid data or invalid data. The reception unit receives deletion information including a logical address indicative of data to be deleted in the erase unit area.

Abstract: A memory system includes a volatile first storing unit, a nonvolatile second storing unit in which data is managed in a predetermined unit, and a controller that writes data requested by a host apparatus in the second storing unit via the first storing unit and reads out data requested by the host apparatus from the second storing unit to the first storing unit and transfers the data to the host apparatus. The controller includes a management table for managing the number of failure areas in a predetermined unit that occur in the second storing unit and switches, according to the number of failure areas, an operation mode in writing data in the second storing unit from the host apparatus.

Abstract: A semiconductor storage device includes word lines extending in first and second directions, and separated from each other in a third direction, sense amplifier circuits that partially overlap the word lines in the third direction, memory strings intersecting the word lines and extending in the third direction, memory-side bit lines extending in the first direction, separated from each other in the second direction, and including first and second adjacent memory-side bit lines, circuit-side bit lines between the word lines and the sense amplifier circuits and partially overlapping the respective memory-side bit lines in the third direction, and contact plugs extending in the third direction and respectively connecting the memory-side bit lines and the circuit-side bit lines. The contact plugs include first and second contract plugs that are electrically connected to the first and second memory-side bit lines, respectively, and are not aligned along the first or second direction.

Abstract: A method of generating soft decision detection parameters for a plurality of received signals. The method comprises defining a hard decision boundary and a plurality of quantisation intervals wherein each quantisation interval extends from the hard decision boundary by an interval distance, selecting a log likelihood value from a set of log likelihood values for each received signal based on the quantisation interval in which the received signal is detected, performing a soft decoding using a plurality of log likelihood values, adjusting the set of log likelihood values based on a result of the soft decoding, determining an error probability for a quantisation interval, comparing the error probability against a target error probability and adjusting the interval distance in order to obtain the target error probability.

Abstract: A storage device according to embodiments includes a substrate, a stacked body, a first region, a second region, and first to nth electrodes. The stacked body is provided on the substrate and having first to nth (n is an integer of 3 or more) conductive layers stacked in a direction perpendicular to a surface of the substrate. The first region includes a part of the stacked body, and has a first step structure including the first to the nth conductive layers. The second region includes a part of the stacked body, and has a second step structure different from the first step structure including at least a part of the first to nth conductive layers. The first to nth electrodes are provided in the first region and connected to the first to nth conductive layers and extend in a direction perpendicular to the surface of the substrate.