Patents Assigned to Memory Corporation
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Publication number: 20210114284Abstract: According to an embodiment, an imprint method includes applying a resist above a substrate, and bringing a template having a concave-convex pattern into contact with the resist. Then, the imprint method includes positioning the template and the substrate with respect to each other, while monitoring an alignment mark provided on the template and an alignment mark provided on the substrate, by using an optical monitor under a state where the template is set in contact with the resist. Further, the imprint method includes monitoring a filling state of the resist into a recessed pattern provided on the template, by using the optical monitor under a state where the template is set in contact with the resist.Type: ApplicationFiled: December 29, 2020Publication date: April 22, 2021Applicant: Toshiba Memory CorporationInventor: Masafumi ASANO
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Publication number: 20210118514Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell. The control unit controls write, read, and erase of the nonvolatile semiconductor memory device. The control unit changes the read level between a start of use of the nonvolatile semiconductor memory device and a timing after an elapse of a time.Type: ApplicationFiled: December 30, 2020Publication date: April 22, 2021Applicant: Toshiba Memory CorporationInventor: Hiroyuki NAGASHIMA
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Publication number: 20210118898Abstract: According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.Type: ApplicationFiled: December 7, 2020Publication date: April 22, 2021Applicant: Toshiba Memory CorporationInventors: Yoshiaki FUKUZUMI, Hideaki AOCHI, Mie MATSUO, Kenichiro YOSHII, Koichiro SHINDO, Kazushige KAWASAKI, Tomoya SANUKI
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Patent number: 10985181Abstract: According to one embodiment, a source layer includes a semiconductor layer including an impurity. A stacked body includes a plurality of electrode layers stacked with an insulator interposed. A gate layer is provided between the source layer and the stacked body. The gate layer is thicker than a thickness of one layer of the electrode layers. A semiconductor body extends in a stacking direction of the stacked body through the stacked body and the gate layer. The semiconductor body further extends in the semiconductor layer where a side wall portion of the semiconductor body contacts the semiconductor layer. The semiconductor body does not contact the electrode layers and the gate layer.Type: GrantFiled: April 9, 2020Date of Patent: April 20, 2021Assignee: Toshiba Memory CorporationInventor: Shinya Arai
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Publication number: 20210111189Abstract: According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first electrodes, a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and a memory film provided between each of the first electrodes and the semiconductor layer. The semiconductor layer includes a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode. The second portion has a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction.Type: ApplicationFiled: December 21, 2020Publication date: April 15, 2021Applicant: Toshiba Memory CorporationInventors: Takashi ISHIDA, Yoshiaki FUKUZUMI, Takayuki OKADA, Masaki TSUJI
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Publication number: 20210110874Abstract: According to one embodiment, a memory system includes a semiconductor memory device and a controller. The device includes a plurality of memory cells capable of storing at least first to third data and a word line coupled to the plurality of memory cells. The first data is determined by a first read operation including a first read level. The second data is determined by a second read operation including a second read level. The third data is determined by a third read operation including a third read level. The controller controls the semiconductor memory device to perform a forth read operation including the first and second read levels in a search operation for first to third read voltages corresponding to the first to third read levels, respectively.Type: ApplicationFiled: December 22, 2020Publication date: April 15, 2021Applicant: Toshiba Memory CorporationInventors: Masanobu SHIRAKAWA, Tsukasa TOKUTOMI, Marie TAKADA
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Patent number: 10978165Abstract: According to one embodiment, a memory system includes a non-volatile semiconductor memory that includes a memory cell and a controller having a memory storing a write parameter used in a write operation to the memory cell. The controller instructs the non-volatile semiconductor memory to perform the write operation to the memory cell using the write parameter, receives, from the non-volatile semiconductor memory, a result of checking of the write parameter which is obtained in the write operation and updates the write parameter stored in the memory on the basis of the result of checking of the write parameter.Type: GrantFiled: June 10, 2019Date of Patent: April 13, 2021Assignee: Toshiba Memory CorporationInventors: Suguru Nishikawa, Yoshihisa Kojima, Masanobu Shirakawa
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Publication number: 20210104282Abstract: According to an embodiment, a semiconductor memory, on receiving a first command, applies a voltage within a first range and a voltage within a second range to a word line and reads a first bit from a memory cell, and, on receiving a second command, applies a voltage within a third range to the word line and reads a second bit from the memory cell. The controller issues the first command a plurality of times and changes the voltages to be applied to the word line within the first range and the second range in accordance with the plurality of first commands, specifies a first and second voltage within the first and the second range, respectively, and estimates a third voltage within the third range. The voltage applied to read the second bit is the estimated third voltage.Type: ApplicationFiled: December 18, 2020Publication date: April 8, 2021Applicant: Toshiba Memory CorporationInventors: Tsukasa TOKUTOMI, Masanobu SHIRAKAWA, Marie TAKADA
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Publication number: 20210103390Abstract: A memory system includes a volatile first storing unit, a nonvolatile second storing unit in which data is managed in a predetermined unit, and a controller that writes data requested by a host apparatus in the second storing unit via the first storing unit and reads out data requested by the host apparatus from the second storing unit to the first storing unit and transfers the data to the host apparatus. The controller includes a management table for managing the number of failure areas in a predetermined unit that occur in the second storing unit and switches, according to the number of failure areas, an operation mode in writing data in the second storing unit from the host apparatus.Type: ApplicationFiled: December 17, 2020Publication date: April 8, 2021Applicant: Toshiba Memory CorporationInventors: Junji YANO, Hidenori MATSUZAKI, Kosuke HATSUDA
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Patent number: 10971512Abstract: According to one embodiment, a semiconductor memory device includes a stacked body, memory pillars, first and second insulation layers and an isolation region. The stacked body above a substrate includes conductive layers isolated from each other and stacked along a first direction crossing the substrate surface. The memory pillars extend through the stacked body along the first direction. The first insulation layer is provided above the memory pillars. The isolation region is provided higher than upper surfaces of the memory pillars in the stacked body along the first direction, and isolates the stacked body in a second direction crossing the first direction. The second insulation layer is provided on the first insulation layer and a side wall of the isolation region.Type: GrantFiled: March 30, 2020Date of Patent: April 6, 2021Assignee: Toshiba Memory CorporationInventor: Hidenobu Nagashima
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Publication number: 20210096949Abstract: According to an embodiment, a memory controller obtains first data in a first page using a first voltage, obtains a first shift amount based on a first and second number. The first and second numbers represent numbers of bits each of which has different values in a first and second manner between the first data and first expected data. The controller obtains second data in the second page using a second voltage and a second shift amount, and obtains a third shift amount based on a third and fourth number, the third and fourth numbers respectively represent numbers of bits each of which has different values in the first and second manner between the second data and second expected data.Type: ApplicationFiled: November 6, 2020Publication date: April 1, 2021Applicant: Toshiba Memory CorporationInventors: Kengo KUROSE, Masanobu SHIRAKAWA, Marie TAKADA
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Patent number: 10965324Abstract: According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.Type: GrantFiled: May 22, 2019Date of Patent: March 30, 2021Assignee: Toshiba Memory CorporationInventors: Riki Suzuki, Toshikatsu Hida, Osamu Torii, Hiroshi Yao, Kiyotaka Iwasaki
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Patent number: 10963338Abstract: A flash memory system may include a flash memory and a circuit for performing operations of the flash memory. The circuit may be configured to estimate slope information of a plurality of threshold voltage samples based on soft decoding errors in connection with a first read operation on the flash memory. The circuit may be further configured to generate estimated soft information based on the estimated slope information. The circuit may be further configured to decode a result of a second read operation on the flash memory based on the estimated soft information.Type: GrantFiled: September 12, 2019Date of Patent: March 30, 2021Assignee: Toshiba Memory CorporationInventors: Avi Steiner, Hanan Weingarten
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Patent number: 10964671Abstract: A semiconductor device includes first and second chips that are stacked such that first surfaces of their element layers face each other. Each chip has a substrate, an element layer on a first surface of the substrate, pads on the element layer, and vias that penetrate through the substrate and the element layer. Each via is exposed from a second surface of the substrate and directly connected to one of the pads. The vias include a first via of the first chip directly connected to a first pad of the first chip and a second via of the second chip directly connected to a second pad of the second chip. The pads further include a third pad of the second chip which is electrically connected to the second pad by a wiring in the element layer of the second chip and to the first pad through a micro-bump.Type: GrantFiled: February 27, 2019Date of Patent: March 30, 2021Assignee: Toshiba Memory CorporationInventor: Masaru Koyanagi
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Patent number: 10964712Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.Type: GrantFiled: November 14, 2019Date of Patent: March 30, 2021Assignee: Toshiba Memory CorporationInventors: Takehiko Amaki, Yoshihisa Kojima, Toshikatsu Hida, Marie Grace Izabelle Angeles Sia, Riki Suzuki, Shohei Asami
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Patent number: 10962657Abstract: According to one embodiment, a superconducting element used as a pixel for detecting a particle is disclosed. The superconducting element includes at least one superconducting strip. The at least one superconducting strip includes a meandering structure. The meandering structure includes a first portion extending in a first direction and made of a superconducting material, a second portion connected to the first portion, extending in a second direction perpendicular to the first direction, and being conductive, and a third portion connected to the second portion, extending in a direction opposite to the first direction, and made of a superconducting material. A superconducting region of any one of the first portion and the third portion is configured to be divided when the particle is radiated to the first portion.Type: GrantFiled: July 2, 2019Date of Patent: March 30, 2021Assignee: Toshiba Memory CorporationInventor: Takeshi Yamane
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Patent number: 10964632Abstract: According to one embodiment, there is provided a semiconductor device including a substrate, a semiconductor chip, and a conductive film. The substrate has a main face. The semiconductor chip has a surface equipped with an SRAM circuit. The semiconductor chip is mounted on the main face via a plurality of bump electrodes in a state where the surface faces the main face. The conductive film is disposed on the main face or the surface. The conductive film extends planarly between the plurality of bump electrodes. A region in the main face or the surface where the conductive film is disposed overlaps the SRAM circuit in a direction perpendicular to the main face.Type: GrantFiled: September 9, 2019Date of Patent: March 30, 2021Assignee: Toshiba Memory CorporationInventors: Takeshi Fujimori, Soichiro Ibaraki, Shinji Yamashita
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Publication number: 20210091116Abstract: A plurality of semiconductor layers have longitudinally a first direction, have a peripheral area surrounded by the plurality of control gate electrodes, and are arranged in a plurality of rows within the laminated body. A controller controls a voltage applied to the control gate electrodes and bit lines. The controller, during a writing operation, applies a first voltage to a first bit line connected to the semiconductor layer positioned in a first row closer to the insulation separating layer, and applies a second voltage larger than the first voltage to a second bit line connected to the semiconductor layer positioned in a second row positioned further from the insulation separating layer with respect to the first row, among the plurality of rows.Type: ApplicationFiled: December 7, 2020Publication date: March 25, 2021Applicant: Toshiba Memory CorporationInventor: Yasuhiro SHIMURA
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Publication number: 20210090616Abstract: A data latch circuit includes a first n-channel transistor and a first p-channel transistor. A gate of the first n-channel transistor and a gate of the first p-channel transistor are a common gate.Type: ApplicationFiled: December 2, 2020Publication date: March 25, 2021Applicant: Toshiba Memory CorporationInventors: Keisuke NAKATSUKA, Tomoya SANUKI, Takashi MAEDA, Go SHIKATA, Hideaki AOCHI
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Patent number: 10957710Abstract: According to one embodiment, a semiconductor memory includes a plurality of conductors stacked with insulators being interposed therebetween and a pillar through the plurality of conductors. The pillar includes a first columnar section, a second columnar section, and a joint portion between the first columnar section and the second columnar section. The pillar comprises portions that cross the respective conductors and that each function as part of a transistor. The plurality of conductors include a first conductor. The first conductor is closest to the joint portion among the plurality of conductors through the second columnar section, and includes a bending portion formed along the joint portion.Type: GrantFiled: July 23, 2020Date of Patent: March 23, 2021Assignee: Toshiba Memory CorporationInventor: Hideto Takekida
