Patents Assigned to Memory Corporation
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Publication number: 20210202526Abstract: According to one embodiment, a semiconductor memory device includes a stacked body which is provided on a substrate and in which an insulating film and an electrode film are alternately stacked. The semiconductor memory device also includes an insulating member which penetrates the stacked body in a stacking direction of the insulating film and the electrode film to thereby separate the stacked body. The semiconductor memory device also includes a semiconductor pillar which penetrates the stacked body in the stacking direction. A maximum portion of the insulating member where a first distance from a side surface of the insulating member to a central plane of the insulating member becomes maximum and a maximum portion of the semiconductor pillar where a second distance from a side surface of the semiconductor pillar to a center line of the semiconductor pillar becomes maximum being provided in different positions in the stacking direction.Type: ApplicationFiled: March 17, 2021Publication date: July 1, 2021Applicant: Toshiba Memory CorporationInventor: Kotaro NODA
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Publication number: 20210202523Abstract: According to one embodiment, a source layer includes a semiconductor layer including an impurity. A stacked body includes a plurality of electrode layers stacked with an insulator interposed. A gate layer is provided between the source layer and the stacked body. The gate layer is thicker than a thickness of one layer of the electrode layers. A semiconductor body extends in a stacking direction of the stacked body through the stacked body and the gate layer. The semiconductor body further extends in the semiconductor layer where a side wall portion of the semiconductor body contacts the semiconductor layer. The semiconductor body does not contact the electrode layers and the gate layer.Type: ApplicationFiled: March 15, 2021Publication date: July 1, 2021Applicant: Toshiba Memory CorporationInventor: Shinya ARAI
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Publication number: 20210202263Abstract: According to an embodiment, a nonvolatile semiconductor memory device comprises a plurality of conductive layers that are stacked in plurality in a first direction via an inter-layer insulating layer, that extend in a second direction which intersects the first direction, and that are disposed in plurality in a third direction which intersects the first direction and the second direction. In addition, the same nonvolatile semiconductor memory device comprises: a semiconductor layer that has the first direction as a longitudinal direction; a tunnel insulating layer that contacts a side surface of the semiconductor layer; a charge accumulation layer that contacts a side surface of the tunnel insulating layer; and a block insulating layer that contacts a side surface of the charge accumulation layer. Furthermore, in the same nonvolatile semiconductor memory device, an end in the third direction of the plurality of conductive layers is rounded.Type: ApplicationFiled: February 24, 2021Publication date: July 1, 2021Applicant: Toshiba Memory CorporationInventors: Takeshi SONEHARA, Takahiro HIRAI, Masaaki HIGUCHI, Takashi SHIMIZU
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Publication number: 20210202524Abstract: A semiconductor memory device includes first structure bodies and second structure bodies arranged alternately along a first direction. The first structure body includes electrode films arranged along a second direction. The second structure body includes columnar members, first insulating members, and second insulating members. The columnar member includes a semiconductor member extending in the second direction and a charge storage member provided between the semiconductor member and the electrode film. The second insulating members are arranged along a third direction. Lengths in the first direction of the second insulating members are longer than lengths in the first direction of the first insulating members. Positions of the second insulating members in the third direction are different from each other between the second structure bodies adjacent to each other in the first direction. The columnar members and the first insulating members are arranged alternately between the second insulating members.Type: ApplicationFiled: March 15, 2021Publication date: July 1, 2021Applicant: Toshiba Memory CorporationInventor: Keisuke NAKATSUKA
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Patent number: 11049878Abstract: A semiconductor memory device includes a semiconductor substrate including a diode formed in an upper layer portion of the semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film and coupled to the diode, a stacked body provided above the first conductive film, an insulator and an electrode film being stacked alternately in the stacked body, a semiconductor member piercing the stacked body and being connected to the first conductive film, and a charge storage member provided between the electrode film and the semiconductor member.Type: GrantFiled: July 14, 2020Date of Patent: June 29, 2021Assignee: Toshiba Memory CorporationInventors: Jun Fujiki, Shinya Arai, Kotaro Fujii
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Patent number: 11049808Abstract: A semiconductor storage device of an embodiment includes: a stacked body in which a plurality of conductive layers are stacked with an insulating layer interposed therebetween, the stacked body having a memory portion in which a plurality of memory cells are disposed and a stepped portion in which ends of the plurality of conductive layers form a step shape; and a conductive portion which extends in the memory portion in a stacking direction of the stacked body inside the plurality of conductive layers from an uppermost conductive layer among the plurality of conductive layers, extends in the stepped portion in the stacking direction of the stacked body inside at least some layers among the plurality of conductive layers, and extends from the memory portion to the stepped portion in a direction intersecting the stacking direction of the stacked body. A height of the conductive portion in the stepped portion is lower than a height of the conductive portion in the memory portion.Type: GrantFiled: July 8, 2019Date of Patent: June 29, 2021Assignee: Toshiba Memory CorporationInventor: Hisashi Nishimura
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Patent number: 11049581Abstract: A method of managing errors in a plurality of storage drives includes receiving, at a memory controller coupled to at least one storage medium in an SSD, a read command from a host interface. The method also includes retrieving, from the storage medium, read data corresponding to a plurality of data chunks to be retrieved in response to the read command, and determining that at least one data chunk of the plurality of data chunks is unable to be read, the at least one data chunk corresponding to a failed data chunk. And in response to determining the failed data chunk, sending to the host interface the read data including the failed data chunk or excluding the failed data chunk. And in response to the read command sending to the host interface status information about all data chunks.Type: GrantFiled: March 6, 2020Date of Patent: June 29, 2021Assignee: Toshiba Memory CorporationInventors: Neil Buxton, Shigehiro Asano, Steven Wells, Mark Carlson
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Patent number: 11049870Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a memory cell array, first circuitry and a via. The semiconductor substrate includes a first main surface and a second main surface opposite the first main surface. The memory cell array is provided on the first main surface. The memory cell array includes stacked memory cells. The first circuitry is provided on the second main surface. The first circuitry is configured to operate the memory cells. The via penetrates through the semiconductor substrate. The via provides electrical connection between the memory cells and the first circuitry.Type: GrantFiled: March 11, 2019Date of Patent: June 29, 2021Assignee: Toshiba Memory CorporationInventor: Tsuyoshi Sugisaki
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Patent number: 11049868Abstract: A semiconductor memory device according to an embodiment, includes a plurality of semiconductor pillars extending in a first direction and being arranged along a second direction crossing the first direction, two interconnects extending in the second direction and being provided on two sides of the plurality of semiconductor pillars in a third direction crossing the first direction and the second direction, and an electrode film disposed between each of the semiconductor pillars and each of the interconnects. The two interconnects are drivable independently from each other.Type: GrantFiled: September 15, 2017Date of Patent: June 29, 2021Assignee: Toshiba Memory CorporationInventors: Satoshi Nagashima, Tatsuya Kato, Wataru Sakamoto
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Patent number: 11049571Abstract: According to one embodiment, a semiconductor memory device includes a first conductor extending in a first direction, bit lines, sense amplifiers, and a second conductor extending in the first direction. A plurality of first memory cells being connected to the first conductor. The bit lines respectively connected to the first memory cells. The first sense amplifiers are respectively connected to a plurality of first bit lines included in the bit lines, each of the first sense amplifiers including a first sense node, and a first transistor connected between the first sense node and a corresponding one of the first bit lines. The second conductor function as gate electrodes of the first transistors included in the first sense amplifiers.Type: GrantFiled: November 12, 2019Date of Patent: June 29, 2021Assignee: Toshiba Memory CorporationInventor: Kosuke Yanagidaira
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Patent number: 11048312Abstract: A system and method for controlling a SSD in response to a power failure event of a main power supply to the SSD. The method includes receiving and storing write commands and associated data payloads for execution on the SSD in volatile memory, detecting the power failure event on the SSD, supplying backup power to the SSD during the power failure event, and executing one or more write commands stored in the volatile memory by storing the associated data payloads in a non-volatile memory on the SSD using the backup power. In response to the execution, removing the one or more write commands from the cache such that one or more unexecuted write commands and the associated data payloads remain in the cache, and storing a list of the one or more unexecuted write commands, but not the associated data payloads, in non-volatile memory using the backup power.Type: GrantFiled: February 13, 2019Date of Patent: June 29, 2021Assignee: Toshiba Memory CorporationInventors: Steven Wells, Robert Reed
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Patent number: 11049867Abstract: According to embodiments, a semiconductor memory device includes a plurality of control gate electrodes laminated above a substrate and extend in a first direction and a second direction, and a memory pillar that has one end connected to the substrate, has longitudinally a third direction intersecting with the first direction and the second direction, and is opposed to the plurality of control gate electrodes. The memory pillar includes a core insulating layer and a semiconductor layer arranged around the core insulating layer. The semiconductor layer includes a first portion and a second portion positioned at a substrate side of the first portion. A width in the first direction or the second direction of the semiconductor layer at at least a part of the first portion is larger than a width in the first direction or the second direction of the second portion.Type: GrantFiled: August 4, 2016Date of Patent: June 29, 2021Assignee: Toshiba Memory CorporationInventor: Yasuhiro Shimura
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Patent number: 11042305Abstract: According to one embodiment, a memory system manages wear of each of a plurality of blocks in a nonvolatile memory. The memory system receives, from a host, a write request including a parameter specifying a data retention term required for first data to be written. The memory system selects, from the blocks, a first block in which a data retention term estimated from the wear of the first block is longer than or equal to the specified data retention term. The memory system writes the first data to the first block.Type: GrantFiled: June 11, 2018Date of Patent: June 22, 2021Assignee: Toshiba Memory CorporationInventors: Shinichi Kanno, Hideki Yoshida
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Patent number: 11042322Abstract: A method of managing writing data to a Solid State Drive (SSD). The method includes determining a remaining capacity of an event queue for queuing write commands for execution by the SSD. Dynamically setting an ingress throttle rate of write commands, transferred from a host interface to the event queue based on the remaining capacity of the event queue, during the operation of then SSD and transferring the write commands to the event queue at ingress throttle rate. The method also includes inputting write data associated with the write commands into a write data buffer.Type: GrantFiled: September 13, 2019Date of Patent: June 22, 2021Assignee: Toshiba Memory CorporationInventors: Sebastian Troy, Brian Clarke
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Patent number: 11042300Abstract: In an example, a method of processing commands for a non-volatile storage device includes storing the commands among a plurality of first-level queues in a random access memory (RAM). Each command is assigned to a first-level queue based on membership in one of a plurality of first-level categories. The method further includes removing selected commands from the plurality of first-level queues according to a first schedule and performing at least one operation on the selected commands. The method further includes storing the selected commands among a plurality of second-level queues in the RAM. Each selected command is assigned to a second-level queue based on whether the command is a read command or a write command. The method further includes removing active commands from the plurality of second-level queues according to a second schedule. The method further includes issuing the active commands to a back end of the controller for processing.Type: GrantFiled: March 31, 2015Date of Patent: June 22, 2021Assignee: Toshiba Memory CorporationInventors: Sancar Kunt Olcay, Dishi Lai
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Patent number: 11042411Abstract: A resource management system in a data center one or more data storage resource providers and a transaction server. The transaction server is configured to receive, from a client, a request for read and/or write access for a data storage resource, the request comprising one or more specifications, to provide, to the one or more data storage resource providers, at least a portion of the request, and to receive, from the one or more data storage resource providers, respective responses to the request, the responses respectively comprising one or more allocation options. The transaction server is further configured to select one of the one or more allocation options for registration, and register the selected allocation option with a data manager. At least one of the one or more data storage providers is configured to provide the data storage resource in accordance with the registered allocation option.Type: GrantFiled: March 15, 2019Date of Patent: June 22, 2021Assignee: Toshiba Memory CorporationInventor: Yaron Klein
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Patent number: 11042487Abstract: According to one embodiment, a memory system receives a write request specifying a first logical address to which first data is to be written, and a length of the first data, from a host. The memory system writes the first data to a nonvolatile memory, and stores a first physical address indicating a physical storage location on the nonvolatile memory to which the first data is written, and the length of the first data, in an entry of a logical-to-physical address translation table corresponding to the first logical address. When the memory system receives a read request specifying the first logical address, the memory system acquires the first physical address and the length from the address translation table, and reads the first data from the nonvolatile memory.Type: GrantFiled: August 29, 2019Date of Patent: June 22, 2021Assignee: Toshiba Memory CorporationInventors: Hideki Yoshida, Shinichi Kanno
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Publication number: 20210183877Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.Type: ApplicationFiled: February 23, 2021Publication date: June 17, 2021Applicant: Toshiba Memory CorporationInventors: Takehiko AMAKI, Yoshihisa KOJIMA, Toshikatsu HIDA, Marie Grace Izabelle Angeles SIA, Riki SUZUKI, Shohei ASAMI
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Publication number: 20210183881Abstract: According to one embodiment, a semiconductor memory device includes a stacked body, memory pillars, first and second insulation layers and an isolation region. The stacked body above a substrate includes conductive layers isolated from each other and stacked along a first direction crossing the substrate surface. The memory pillars extend through the stacked body along the first direction. The first insulation layer is provided above the memory pillars. The isolation region is provided higher than upper surfaces of the memory pillars in the stacked body along the first direction, and isolates the stacked body in a second direction crossing the first direction. The second insulation layer is provided on the first insulation layer and a side wall of the isolation region.Type: ApplicationFiled: February 24, 2021Publication date: June 17, 2021Applicant: Toshiba Memory CorporationInventor: Hidenobu NAGASHIMA
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Publication number: 20210175907Abstract: According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.Type: ApplicationFiled: February 18, 2021Publication date: June 10, 2021Applicant: Toshiba Memory CorporationInventors: Riki SUZUKI, Toshikatsu HIDA, Osamu TORII, Hiroshi YAO, Kiyotaka IWASAKI