Patents Assigned to Micronics
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Patent number: 12379860Abstract: A front-end firmware component of a memory sub-system receives a first request to perform a first set of initialization operations and initiates a first set of initialization operations for the front-end component in parallel with initiating a second set of initialization operations for a back-end component. Responsive to completing the first set of initialization operations, the front-end component sends a first notification to a host computer system to indicate that the front-end component is available to respond to requests for configuration data associated with the memory sub-system, receives a second request from the host computer system for a configuration data associated with the memory sub-system, and responsive to receiving the second request from the host computer system before the back-end component has completed the second set of initialization operations, provides the configuration data to the host computer system.Type: GrantFiled: April 4, 2024Date of Patent: August 5, 2025Assignee: Micron Technology, Inc.Inventors: Ximin Shan, Venkata Naga Lakshman Pasala, Noorshaheen Mavungal Noorudheen
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Patent number: 12381735Abstract: The disclosed embodiments are related to securely updating a semiconductor device and in particular to a key management system. In one embodiment, a method is disclosed comprising receiving a request for an activation code database from a remote computing device, the request including at least one parameter; retrieving at least one pair based on the at least one parameter, the pair including a unique ID (UID) and secret key; generating an activation code for the UID; and returning the activation code to the remote computing device.Type: GrantFiled: August 11, 2023Date of Patent: August 5, 2025Assignee: Micron Technology, Inc.Inventor: Lance W. Dover
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Patent number: 12379915Abstract: In some implementations, a host processor associated with a vehicle may select, from a plurality of devices that are configured to communicate with the host processor for performing security functions, a first device to serve as a primary device and a second device to serve as a secondary device. The first device may include a first memory with an embedded hardware security module and may be associated with a first set of nodes of the vehicle. The second device may include a second memory with an embedded hardware security module and may be associated with a second set of nodes of the vehicle. The host processor may determine, based on a signal, a failure associated with the first device or the second device. The host processor may initiate a remediation process based on the failure associated with the first device or the second device. Numerous other implementations are described.Type: GrantFiled: July 6, 2022Date of Patent: August 5, 2025Assignee: Micron Technology, Inc.Inventor: Sourin Sarkar
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Patent number: 12380323Abstract: The disclosed embodiments are related to storing critical data in a memory device such as Flash or DRAM memory device. In one embodiment, a device comprising a plurality of parallel processors is disclosed, the plurality of parallel processors configured to: perform a search and match operation, the search and match operation loading a plurality of synaptic identifier bit strings and a plurality of spike identifier bit strings, the search and match operation further generating a plurality of bitmasks; perform a synaptic integration phase, the synaptic integration phase generating a plurality of synaptic current vectors based on the plurality of bitmasks, the synaptic current vectors associated with respective synthetic neurons; solve a neural membrane equation for each of the synthetic neurons; and update membrane potentials associated with the synthetic neurons, the membrane potentials stored in a memory device.Type: GrantFiled: May 28, 2021Date of Patent: August 5, 2025Assignee: Micron Technology, Inc.Inventor: Dmitri Yudanov
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Patent number: 12381717Abstract: Methods, systems, and devices for techniques for generating a shared secret for an electronic system are described. A memory system may identify an initial key pair and exchange a public key of the key pair with a public key associated with a server. The memory system and the server may each generate a shared secret. In some cases, the memory system and the server may use the shared secret to generate a device identifier for the memory system, for example by incorporating the device identifier into a cryptographic representation of a software layer of the memory system. The memory system and the server may use the device identifier to generate one or more asymmetric key pairs, which may be used by the server to authenticate the memory system.Type: GrantFiled: July 13, 2023Date of Patent: August 5, 2025Assignee: Micron Technology, Inc.Inventor: Lance W. Dover
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Patent number: 12379864Abstract: Aspects of the present disclosure configure a system component, such as memory sub-system controller, to perform empty page scan operations. The controller selects a portion of the set of memory components that is empty and ready to be programmed. The controller reads one or more signals from the selected portion of the set of memory components. The controller generates an error count value representing whether the portion of the set of memory components is valid for programming based on a result of reading the one or more signals from the selected portion. The controller updates a scan frequency for performing the empty page scan operations for the portion of the set of memory components based on the error count value.Type: GrantFiled: March 26, 2024Date of Patent: August 5, 2025Assignee: Micron Technology, Inc.Inventors: Peng Zhang, Murong Lang, Christina Papagianni, Zhenming Zhou
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Patent number: 12381702Abstract: Examples described herein include apparatuses and methods for full duplex device-to-device cooperative communication. Example systems described herein may include self-interference noise calculators. The output of a self-interference noise calculator may be used to compensate for the interference experienced due to signals transmitted by another antenna of the same wireless device or system. In implementing such a self-interference noise calculator, a selected wireless relaying device or wireless destination device may operate in a full-duplex mode, such that relayed messages may be transmitted as well as information from other sources or destinations during a common time period (e.g., symbol, slot, subframe, etc.).Type: GrantFiled: July 8, 2022Date of Patent: August 5, 2025Assignee: MICRON TECHNOLOGY, INC.Inventors: Fa-Long Luo, Tamara Schmitz, Jeremy Chritz, Jaime Cummins
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Patent number: 12381131Abstract: Systems and methods for a semiconductor device having a front-end-of-line structure are provided. The semiconductor device may include a dielectric material having a backside formed on a front side of a semiconductor substrate material and a front side, and an interconnect structure extending through the dielectric material. The interconnect structure may be electrically connected to a semiconductor memory array proximate the front side of the dielectric material. The semiconductor device may further have an insulating material encasing at least a portion of the semiconductor memory array and an opening created during back-end-of-line processing through which the active contact surface at the backside of the interconnect structure is exposed for electrical connection.Type: GrantFiled: November 13, 2023Date of Patent: August 5, 2025Assignee: Micron Technology, Inc.Inventors: Kyle K. Kirby, Kunal R. Parekh
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Patent number: 12380930Abstract: Methods and apparatuses for thin film transistors and related fabrication techniques are described. The thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. The fabrication techniques may use one or more patterns of vias formed at a top layer of a composite stack, which may facilitate building the thin film transistors within the composite stack while using a reduced number of processing steps. Different configurations of the thin film transistors may be built using the fabrication techniques by utilizing different groups of the vias. Further, circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors as described herein along with related via-based fabrication techniques.Type: GrantFiled: November 30, 2023Date of Patent: August 5, 2025Assignee: Micron Technology, Inc.Inventors: Hernan A. Castro, Stephen W. Russell, Stephen H. Tang
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Patent number: 12380931Abstract: Control logic in a memory device receives, from a requestor, a request to read data from the memory array, the request comprising an indication of a segment of the memory array where the data is stored and performs, using previously configured read operation parameters, a first read operation to read the data and a write temperature associated with the data from the memory array. The control logic determines whether the previously configured read operation parameters satisfy a temperature criterion and responsive to determining that the previously configured read operation parameters do not satisfy the temperature criterion, configures the memory device with updated read operation parameters, and performs, using the updated read operation parameters, a second read operation to read the data from the memory array.Type: GrantFiled: August 24, 2023Date of Patent: August 5, 2025Assignee: Micron Technology, Inc.Inventors: Andrea Giovanni Xotta, Umberto Siciliani, Tommaso Vali
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Patent number: 12379867Abstract: A storage product manufactured as a computer component and configured to have: a secure memory region to store cryptographic keys; a network interface; a local storage device having a storage capacity accessible via the network interface; and a host interface to be connected to a local host system. The local host system can control access, made via the network interface, to the storage capacity without receiving a portion of storage access messages received in the network interface. The storage product includes an access controller configured to determine whether a message, received in the network interface from the computer network or in the host interface from the local host system, has a valid verification code according to the cryptographic keys; and if not, the message can be rejected, deleted, discarded, or ignored without further processing.Type: GrantFiled: July 15, 2022Date of Patent: August 5, 2025Assignee: Micron Technology, Inc.Inventor: Luca Bert
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Publication number: 20250245099Abstract: An exemplary system includes a memory comprising an error correction code (ECC) circuit and a scrub circuit, The ECC, during a read operation corresponding to a first read command, detects and corrects an error in read data read from a target row of a memory cell array using an ECC and to provide corrected read data and a ECC error alert (EEA) signal having a value based on a number of errors detected in the read data. The scrub circuit, during the read operation and in response to self-scrub mode being enabled, causes the corrected read data to be written back to the target row of the memory cell array in response to the EEA having a scrub required value.Type: ApplicationFiled: January 25, 2025Publication date: July 31, 2025Applicant: Micron Technology, Inc.Inventors: Graziano MIRICHIGNI, Marco SFORZIN, John NAMKUNG
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Publication number: 20250246221Abstract: An example system includes: a memory chip having a plurality of external terminals; and a controller chip coupled to the plurality of external terminals of the memory chip and configured to issue, via some of the plurality of external terminals, a plurality of commands including a power down entry command and a refresh command. The memory chip is configured to: change an operation mode from a normal mode to a power down mode when the power down entry command is issued from the controller chip; perform a refresh operation when the refresh command is issued from the controller chip in the normal mode; and perform the refresh operation when the controller chip brings one of the plurality of external terminals into a first predetermined level in the power down mode.Type: ApplicationFiled: January 2, 2025Publication date: July 31, 2025Applicant: MICRON TECHNOLOGY, INC.Inventors: Atsushi Hatakeyama, Yoshifumi Mochida
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Patent number: 12374404Abstract: Apparatuses, systems, and methods for algorithm qualifier commands are described according to embodiments of the present disclosure. One example method can include executing an algorithm qualifier command on a memory device and performing an operation on the memory device for a command sequence that follows the algorithm qualifier command using a number of settings indicated by the algorithm qualifier command. The algorithm qualifier command can indicate a number of settings to use while performing the operation on the memory device.Type: GrantFiled: April 22, 2024Date of Patent: July 29, 2025Assignee: Micron Technology, Inc.Inventors: Anna Chiara Siviero, Umberto Siciliani
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Patent number: 12374408Abstract: The present disclosure includes apparatuses, methods, and systems for multi-state programming of memory cells. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of a plurality of possible data states by applying a voltage pulse to the memory cell, determining the memory cell snaps back in response to the applied voltage pulse, turning off a current to the memory cell upon determining the memory cell snaps back, and applying a number of additional voltage pulses to the memory cell after turning off the current to the memory cell.Type: GrantFiled: May 20, 2024Date of Patent: July 29, 2025Assignee: Micron Technology, Inc.Inventors: Jeremy M. Hirst, Shanky K. Jain, Hernan A. Castro, Richard K. Dodge, William A. Melton
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Patent number: 12373347Abstract: Methods, systems, and devices for advanced power off notification for managed memory are described. An apparatus may include a memory array comprising a plurality of memory cells and a controller coupled with the memory array. The controller may be configured to receive a notification indicating a transition from a first state of the memory array to a second state of the memory array. The notification may include a value, the value comprising a plurality of bits and corresponding to a minimum duration remaining until a power supply of the memory array is deactivated. The controller may also execute a plurality of operations according to an order determined based at least in part on a parameter associated with the memory array and receiving the notification comprising the value.Type: GrantFiled: August 30, 2023Date of Patent: July 29, 2025Assignee: Micron Technology, Inc.Inventors: Vincenzo Reina, Binbin Huo
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Patent number: 12373129Abstract: In a computer host system, a system and method to compress the transmission between the central processing unit (CPU) and the dynamic random access memory (DRAM) of either of an extended consecutive series of ‘0’ bits or an extended consecutive series of ‘1’ bits. The CPU or a Compute Express Link (CXL) Initiator associated with the CPU identifies the consecutive strings of ‘0’ bits or ‘1’ bits. The CPU or the CXL Initiator sets data flags in a FLIT data structure, using just two bits or four bits to indicate the strings. The data structure is sent to a CXL memory, which interprets the flags and constructs the extended series of ‘0’ bits or extended series of ‘1’ bits.Type: GrantFiled: July 7, 2023Date of Patent: July 29, 2025Assignee: Micron Technology, Inc.Inventor: Nikesh Agarwal
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Patent number: 12373141Abstract: In some implementations, a device may obtain a command table associated with a memory device, wherein the command table includes one or more entries associated with one or more respective commands, and wherein each entry, from the one or more entries, includes one or more units of data. The device may receive an indication of a modification associated with a first command, wherein the first command indicates a sequence of a first one or more units of data. The device may modify the command table based on the modification associated with the first command, wherein modifying the command table includes at least one of: adding an entry, that indicates the sequence, to the one or more entries to indicate the first command, or removing the entry from the one or more entries. The device may provide, to a controller of the memory device, an indication of the command table.Type: GrantFiled: December 11, 2023Date of Patent: July 29, 2025Assignee: Micron Technology, Inc.Inventor: Dheeraj Dake
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Patent number: 12373144Abstract: The present disclosure includes apparatuses and methods related to a memory apparatus and/or method for addressing in memory with a read identification (RID) number. An example apparatus can include a first memory device, a second memory device coupled to the first memory device, and a controller coupled to the first memory device and the second memory device, wherein the controller is configured to receive a read command requesting data from the first memory device, wherein the read command includes a read identification (RID) number that includes an address to identify a location of the data in the first memory device, and transfer the data from the location in the first memory device to the second memory device in response receiving the read command.Type: GrantFiled: June 14, 2024Date of Patent: July 29, 2025Assignee: Micron Technology, Inc.Inventor: Frank F. Ross
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Patent number: 12374393Abstract: Methods, systems, and devices for varying-polarity read operations for polarity-written memory cells are described. Memory cells may be programmed to store different logic values based on applying write voltages of different polarities to the memory cells. A memory device may read the logic values based on applying read voltages to the memory cells, and the polarity of the read voltages may vary such that at least some read voltages have one polarity and at least some read voltages have another polarity. The read voltage polarity may vary randomly or according to a pattern and may be controlled by the memory device or by a host device for the memory device.Type: GrantFiled: February 23, 2024Date of Patent: July 29, 2025Assignee: Micron Technology, Inc.Inventors: Innocenzo Tortorelli, Hari Giduturi, Fabio Pellizzer