Patents Assigned to Microsystems, Inc.
  • Patent number: 7020161
    Abstract: A system includes a plurality of resources and a plurality of requesters. A first portion of the resources are reserved for a particular time period in the system during a first arbitration phase, in response to prescheduling requests. During a second arbitration phase a second portion of the resources are allocated in response to regular requests, the first portion of the resources which are reserved being unavailable to the regular requests.
    Type: Grant
    Filed: November 16, 2000
    Date of Patent: March 28, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Hans Eberle, Nils Gura
  • Patent number: 7020579
    Abstract: One embodiment of the present invention provides a system that tests the motion performance of an electronic display system, wherein the electronic display system includes a display, graphics processing software, graphics processing circuitry, and an interface coupling the display and the graphics processing circuitry. The system starts by receiving a request to measure an amount of distortion of an object in motion. In response to the request, the system measures the amount of distortion of the object in motion. In a variation on this embodiment, measuring the amount of distortion of the object in motion involves placing a ruler on a boundary of the object where the distortion occurs, increasing the width of the ruler until it covers the distortion, and then measuring the width to determine the size of the distortion.
    Type: Grant
    Filed: November 14, 2003
    Date of Patent: March 28, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Joseph V. Miseli, Eric Boucher
  • Patent number: 7020662
    Abstract: Class of Service (CoS) is a mechanism that allows a user to share attributes between directory entries in a way transparent to an application. A CoS scheme includes a CoS Definition entry and a CoS Template entry. These two entries interact to provide attribute values to target entries within their CoS “scope”. In Classic CoS, an attribute-value pair is matched with a target entry based on the target entry's DN. The CoS Definition entry, which is stored as an LDAP subentry below the branch at which it is effective, identifies the type of CoS being used. The Template entry contains a list of attribute values that are shared. Any change made to the template entry's attribute values is automatically applied to all entries that share the attribute.
    Type: Grant
    Filed: May 29, 2001
    Date of Patent: March 28, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: David Boreham, Peter Rowley
  • Patent number: 7020681
    Abstract: Systems and methods consistent with this invention provide for efficient processing, caching and routing of XML documents through the use of a proxy server. The proxy server is coupled to at least one client computer and a plurality of remote servers on the Internet. The proxy server is adapted in this preferred embodiment to receive a document request in the form of a uniform resource locator (URL) from a client computer and to determine whether the document is an unprocessed XML document. If the document is an unprocessed XML document, the proxy server is further adapted to search a local cache for a processed version of the document, and to transmit the processed document to the requesting client. In the event the document is not found in local storage, the proxy server is adapted to process the XML document, route it to the client and then store the file in local storage in anticipation of subsequent requests for the same document.
    Type: Grant
    Filed: June 14, 2000
    Date of Patent: March 28, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Venkata S. Ayyagari, Polina Kuznetsov
  • Patent number: 7020805
    Abstract: A method for detecting a phantom write error in a data storage system is described. In one embodiment, upon receiving a read command pertaining to a data block stored on a storage medium, two version identifiers associated with the data block are compared. A first version identifier is stored within the data block and a second version identifier is stored outside of the data block. If the version identifiers do not match, the possible occurrence of a phantom write error is detected.
    Type: Grant
    Filed: August 15, 2002
    Date of Patent: March 28, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Nisha D. Talagala, Brian Wong
  • Patent number: 7020699
    Abstract: A system for analyzing test result data from a plurality of test systems capable of producing the test result data in disparate formats is provided. The system includes a data processing block, a memory data structure, and a database. The data processing block is designed to receive the test result data in the disparate formats so as to produce an identifiable result data. The memory data structure is designed to store the identifiable result data in a table format. The database stores the identifiable result data obtained from the memory data structure. The identifiable result data has a uniform format for analyzing the test result data from the plurality of test systems.
    Type: Grant
    Filed: December 19, 2001
    Date of Patent: March 28, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Weiqiang Zhang, Konstantin I. Boudnik
  • Patent number: 7020722
    Abstract: A distributed simulation system includes a plurality of nodes. Each node is configured to simulate a portion of a system under test. The simulation is performed as a series of timesteps. The transition between timesteps is synchronized in the plurality of nodes. In one implementation, the distributed simulation system includes a hub which is configured to synchronize the transition between timesteps in the plurality of nodes. For example, in one embodiment, the hub may receive commands from each of the plurality of nodes. If each command indicates that the corresponding node is capable of completing the timestep, the hub transmits a command to each node indicating that the timestep is complete. The nodes may begin processing the next timestep in response to the command. In other embodiments, a hub may not be included.
    Type: Grant
    Filed: November 9, 2001
    Date of Patent: March 28, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Steven A. Sivier, Carl B. Frankel, Carl Cavanagh, James P. Freyensee
  • Patent number: 7020641
    Abstract: Provided is a method, system, and program for maintaining a database of data objects. A first data object implemented in a first programming language including attributes and attribute values for a class is received. The first data object is transformed to a second data object implemented in a second programming language, wherein the second data object includes the attributes and attribute values of the class included in the first data object. The second data object is added to the database, wherein the database is capable of storing multiple data objects implemented in the second programming language.
    Type: Grant
    Filed: October 22, 2001
    Date of Patent: March 28, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Terence Leong, Mahima Mallikarjuna, Julian S. Taylor
  • Patent number: 7020750
    Abstract: A hybrid system for updating cache including a first computer system coupled to a database accessible by a second computer system, said second computer system including a cache, a cache update controller for concurrently implementing a user defined cache update policy, including both notification based cache updates and periodic based cache updates, wherein said cache updates enforce data coherency between said database and said cache, and a graphical user interface for selecting between said notification based cache updates and said periodic based cache updates.
    Type: Grant
    Filed: September 17, 2002
    Date of Patent: March 28, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Pirasenna Thiyagaranjan, Krishnendu Chakraborty, Peter D. Stout, Xuesi Dong
  • Patent number: 7020779
    Abstract: An e-mail handling system, wherein e-mail messages are entered, transported and stored, comprises a central key repository, means for encrypting a message using a key associated with the message, means for adding the key to the central key repository; and means for deleting the key for a message when the message is to be made unrecallable.
    Type: Grant
    Filed: August 22, 2000
    Date of Patent: March 28, 2006
    Assignee: Sun Microsystems, Inc.
    Inventor: Ivan E. Sutherland
  • Patent number: 7020763
    Abstract: A processing core comprising R-number of processing pipelines each comprising N-number of processing paths. Each of the R-number of processing pipelines are synchronized together to operate as a single very long instruction word (VLIW) processing core. The VLIW processing core is configured to process R×N-number of VLIW sub-instructions in parallel. In addition, the R-number of pipelines can be configured to operate independently as separately operating pipelines. In accordance with one embodiment of the present invention, each of the R-number of processing pipelines comprises S-number of register files, such that the processing core comprises R×S-number of register files. In accordance with another embodiment of the present invention, each of the R-number of processing pipelines comprises one register file for every two of the N-number of processing paths, such that S=N/2.
    Type: Grant
    Filed: March 8, 2001
    Date of Patent: March 28, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Ashley Saulsbury, Michael Parkin, Daniel S. Rice
  • Patent number: 7020146
    Abstract: A method and mechanism for arbitrating and transmitting data. A first transaction and a second transaction are detected. The first transaction is targeted to a first domain and the second transaction is targeted to a second domain different than the first domain. Subsequent to receiving the transactions, arbitration domains corresponding to each are determined. In response to detecting the arbitration domains are not equal, the first and second transaction may be transmitted concurrently. However, if the arbitration domains are determined to be equal, arbitration is performed and transmission of the first and second transactions is serialized. Also contemplated is generating masks corresponding to each of the received transactions. The masks which are generated include an indication of the target domain of the corresponding transaction. When the transaction is conveyed to a port for transmittal, its mask is conveyed as well.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: March 28, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Brian L. Smith, Wayne Seltzer, Andrew Clayton
  • Patent number: 7020870
    Abstract: A method is provided, the method comprising defining an actual size of each variable in a programming language at a declaration time when the actual size of the respective variable can be defined and declaring at least one variable in the programming language to have a dynamic size at the declaration time when the actual size of the at least one variable is not known. The method also comprises defining the actual size of the at least one variable in the programming language when the actual size of the at least one variable becomes known after the declaration time.
    Type: Grant
    Filed: May 15, 2002
    Date of Patent: March 28, 2006
    Assignee: Sun Microsystems, Inc.
    Inventor: Sumit Gupta
  • Patent number: 7020811
    Abstract: A method of testing error correction/detection logic may involve providing each of a set of n data bit combinations to the error correction/detection logic. Each data bit combination has n bits, and the n data bit combinations may be created by creating an initial data bit combination whose data bits have the same logical value and then shifting a bit having the opposite value across the initial data bit combination. In response to being provided with the n data bit combinations, the error correction/detection logic generates a set of check bits for each of the n data bit combinations. The set of check bits generated by the error correction/detection logic for each of the n data bit combinations may then be verified.
    Type: Grant
    Filed: October 29, 2001
    Date of Patent: March 28, 2006
    Assignee: Sun Microsystems, Inc.
    Inventor: James M. Byrd
  • Patent number: 7019965
    Abstract: An ejector mechanism. The ejector mechanism includes an ejector pair, pivotally mounted on a surface of the carrier. Each ejector of the ejector pair comprises an ejector slot that is engageable with an ejector pin that is located on a chassis, which accommodates the carrier. A plurality of gear teeth are configured into each ejector wherein the gear teeth on one ejector engage or disengage with the gear teeth on another ejector as the ejector pair pivotally rotates about a point on the carrier. A handle is affixed to one ejector to facilitate the moving of the ejector pair.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: March 28, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: David M. Bradley, William L. Grouell, Glenn Charest
  • Patent number: 7020802
    Abstract: One embodiment of the present invention provides a system that systematically monitors and records performance parameters for a computer system. During operation, the system periodically measures values for a set of performance parameters associated with the computer system while the computer system continues operating. The system then records the values on a data storage device, wherein the recording process keeps track of temporal relationships between events in different performance parameters. The system subsequently allows the recorded values for the set of performance parameters to be analyzed.
    Type: Grant
    Filed: October 17, 2002
    Date of Patent: March 28, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Kenny C. Gross, Larry G. Votta, Jr.
  • Patent number: 7019999
    Abstract: A content addressable memory (CAM) device including a plurality of CAM cells, a pair of bit lines and a sense amplifier. Each of the plurality of CAM cells includes a static storage circuit to store a data value and is coupled to the pair of bit lines. The sense amplifier includes a first transistor having first and second terminals coupled to first and second bit lines of the pair of bit lines, respectively.
    Type: Grant
    Filed: October 8, 2003
    Date of Patent: March 28, 2006
    Assignee: NetLogic Microsystems, Inc
    Inventors: Varadarajan Srinivasan, Sandeep Khanna, Bindiganavale S. Nataraj
  • Patent number: 7020820
    Abstract: Disclosed are novel methods and apparatus for efficiently providing instruction-based BIST of external memory. In an embodiment, a built-in self-testing system is disclosed. The system includes an external memory module, an on-chip memory controller coupled to the external memory module, an on-chip built-in self-test (BIST) module coupled to the on-chip memory controller, and an interface controller coupled to the BIST module to provide an interface to access the BIST module. The on-chip memory controller may send and receive data to and from the external memory module. And, the BIST module may include an instruction register to store a plurality of instructions.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: March 28, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Olivier Caty, Ismet Bayraktaroglu, Amitava Majumdar
  • Patent number: 7020586
    Abstract: A system and method for designing a data center. For each unique piece of equipment (e.g., a specific type/model of computer server, storage array, communication device) that may be installed in a data center, or each unique configuration of a piece of equipment, an equipment unit (EU) is defined to describe the equipment requirements or characteristics regarding power, cooling, size, weight, connectivity and/or other factors. An interchangeable equipment unit (IEU) may be defined to reflect the worst-case requirements of multiple pieces of equipment that may be interchanged or substituted (e.g., two different storage arrays). The total requirements of a desired equipment layout are determined from the EUs, and may be compared to the capacities of the data center space regarding available power, cooling, physical size, weight restrictions, etc. If any requirements exceed a data center capacity, the equipment or layout may be altered or the data center may be restructured.
    Type: Grant
    Filed: December 17, 2001
    Date of Patent: March 28, 2006
    Assignee: Sun Microsystems, Inc.
    Inventor: Robert D. Snevely
  • Patent number: 7020079
    Abstract: One embodiment of the present invention provides a system for bypassing use of a protocol checksum during communications across a reliable network link. The system operates by configuring a communication system to bypass use of the checksum during communications across the reliable network link. When the system subsequently receives an outbound packet to be transmitted to a destination across the reliable network link, the system sends the outbound packet to the destination without computing the checksum for the outbound packet. In one embodiment of the present invention, upon receiving an inbound packet from a source across the reliable network link, the system accepts the inbound packet without re-computing the checksum, wherein re-computation of the checksum is required by the communication protocol to verify that the inbound packet was received without errors.
    Type: Grant
    Filed: October 23, 2001
    Date of Patent: March 28, 2006
    Assignee: SUN Microsystems, Inc.
    Inventor: Hsiao-Keng J. Chu