Abstract: A super-junction trench MOSFET with Resurf Stepped Oxide and trenched contacts is disclosed. The inventive structure can apply additional freedom for better optimization and manufacturing capability by tuning thick oxide thickness to minimize influence of charge imbalance, trapped charges, etc. . . . Furthermore, the fabrication method can be implemented more reliably with lower cost.

Abstract: A method and system for automating the management of an inventory of consumer items at a consumer location uses a programmed device that accepts input data and executes control logic for automating inventory management. At least one shopping list is received, a shopping list trend is established, and a smart list is generated with the control logic, in accordance with the shopping list trend, such that the smart list predictive of a next shopping list.

Abstract: A hybrid IGBT device having a VIGBT and LDMOS structures comprises at least a drain trenched contact filled with a conductive plug penetrating through an epitaxial layer, and extending into a substrate; a vertical drain region surrounding at least sidewalls of the drain trenched contact, extending from top surface of the epitaxial layer to the substrate, wherein the vertical drain region having a higher doping concentration than the epitaxial layer.

Abstract: A power semiconductor device with improved avalanche capability structures is disclosed. By forming at least an avalanche capability enhancement doped regions with opposite conductivity type to epitaxial layer underneath an ohmic contact doped region which surrounds at least bottom of trenched contact filled with metal plug between two adjacent gate trenches, avalanche current is enhanced with the disclosed structures.

Abstract: A power semiconductor device with improved avalanche capability structures is disclosed. By forming at least an avalanche capability enhancement doped regions with opposite conductivity type to epitaxial layer underneath an ohmic contact doped region which surrounds at least bottom of trenched contact filled with metal plug between two adjacent gate trenches, avalanche current is enhanced with the disclosed structures.

Abstract: A LDMOS with double LDD and trenched drain is disclosed. According to some preferred embodiment of the present invention, the structure contains a double LDD region, including a high energy implantation to form lightly doped region and a low energy implantation thereon to provide a low resistance path for current flow without degrading breakdown voltage. At the same time, a P+ junction made by source mask is provided underneath source region to avoid latch-up effect from happening.

Abstract: A trench MOSFET having shielded gate in parallel with trench Schottky rectifier is formed on a single chip to further increase the efficiency of the trench MOSFET having shielded electrode. As the size of present device is getting smaller and smaller, the trench Schottky rectifier of this invention is able to be shrink and, at the same time, to achieve lower forward voltage drop and lower reverse leakage current.

Abstract: The present invention is to provide a trench MOSFET with an etching buffer layer in a trench gate, comprising: a substrate which has a first surface and a second surface opposite to each other and comprises at least a drain region, a gate region, and a source region which are constructed as a plurality of semiconductor cells with MOSFET effect; a plurality of gate trenches, each of which is extended downward from the first surface and comprises a gate oxide layer covered on a inner surface thereof and a gate conductive layer filled inside, comprised in the gate region; at least a drain metal layer formed on the second surface according to the drain region; at least a gate runner metal layer formed on the first surface according to the gate region; and at least a source metal layer formed on the first surface according to the source region; wherein the gate trenches distinguished into at least a second gate trench formed at a terminal of the source region and at least a first gate trenches wrapped in the sourc

Abstract: A power semiconductor device with improved avalanche capability structures is disclosed. By forming at least an avalanche capability enhancement doped regions with opposite conductivity type to epitaxial layer underneath an ohmic contact doped region which surrounds at least bottom of trenched contact filled with metal plug between two adjacent gate trenches, avalanche current is enhanced with the disclosed structures.

Abstract: A method for manufacturing a trenched semiconductor power device includes a step of forming said semiconductor power device with a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The method further includes the steps of covering the MOSFET cell with an insulation layer and applying a contact mask for opening a source-body contact trench extending through the source and body regions into an epitaxial layer underneath for filling a contact metal plug therein. And, the method further includes a step of forming an embedded Schottky diode by forming a Schottky barrier layer near a bottom of the source-body contact trench below the contact metal plug with the Schottky barrier layer having a barrier height for reducing a leakage current through the embedded Schottky diode during a reverse bias between the drain and the source.

Abstract: A semiconductor power device integrated with a Gate-Source ESD diode for providing an electrostatic discharge (ESD) protection and a Gate-Drain clamp diode for drain-source avalanche protection. The semiconductor power device further includes a Nitride layer underneath the diodes and a thick oxide layer as an etching stopper layer for protecting a thin oxide layer on top surface of body region from over-etching.

Abstract: A semiconductor power device integrated with a Gate-Source ESD diode for providing an electrostatic discharge (ESD) protection and a Gate-Drain clamp diode for drain-source avalanche protection. The semiconductor power device further includes a Nitride layer underneath the diodes and a thick oxide layer as an etching stopper layer for protecting a thin oxide layer on top surface of body region from over-etching.

Abstract: A trench MOSFET structure with ultra high cell density is disclosed, wherein the source regions and the body regions are located in different regions to save the mesa area between every two adjacent gate trenches in the active area. Furthermore, the inventive trench MOSFET is composed of stripe cells to further increase cell packing density and decrease on resistance Rds between the drain region and the source region.

Abstract: Systems and methods for detecting scour. Some embodiments provide systems which include a sensor and a signal generator with a combined density equal to or greater than that of water. Optionally, the sensor can be a magnet, magnetic resonator, or accelerometer. In some embodiments, the sensor is adapted to be placed in regions potentially subject to scour and to sense a scour-related condition. The signal generator generates a wireless signal conveying data regarding the as-sensed scour-related. In some embodiments the sensor is the signal generator while a receiver of the wireless signal can include an antenna, a magnetometer, or an ultrasonic sensor. In some embodiments, the housing is conic and the magnetic object is offset from the center of gravity of the coupled sensor, signal generator and housing.

Abstract: A semiconductor power device integrated with a Gate-Source ESD diode for providing an electrostatic discharge (ESD) protection and a Gate-Drain clamp diode for drain-source avalanche protection. The semiconductor power device further includes a Nitride layer underneath the diodes and a thick oxide layer as an etching stopper layer for protecting a thin oxide layer on top surface of body region from over-etching.

Abstract: A MOSFET with a 0.7˜2.0 micrometers deep trench is formed by first carrying out a processing step of opening a trench in a semiconductor substrate. A thick insulator layer is then deposited in the trench such that the film at the bottom of the trench is much thicker than the sidewall of the trench. The insulator layer at the sidewall is then removed followed by the creation of composite dual layers that form the Gate Oxide. Another embodiment has the insulator layer deposited after Gate Oxide growth and stop at a thin Nitride layer which serves as stop layer during insulator pullback at trench sidewall and during Polysilicon CMP. Embodiments of the present invention eliminates weak spot at trench bottom corner encountered when Gate Oxide is grown in a 0.2 micrometers deep trench with thick bottom oxide.

Abstract: A trench MOSFET device with embedded Schottky rectifier, gate-drain and gate-source diodes on single chip is formed with shallow trench structure to achieve device shrinkage and performance improvement. The present semiconductor devices achieve low Vf and reverse leakage current for embedded Schottky rectifier, have overvoltage protection for GS clamp diodes and avalanche protection for GD clamp diodes. More particularly, gate charge of the present semiconductor device is reduced due to the shallow trench surrounded by an additional N doped area around the bottom while keeping Rds low enough and at the same time, maintaining BV at a certain level.

Abstract: A structure of power semiconductor device having dummy cells around edge of active area is disclosed. The UIS test result of said improved structure shows that failed site after UIS test randomly located in active area which means avalanche capability of the semiconductor power device is enhanced by implementation of the dummy cells.

Abstract: A super-junction trench MOSFET with Resurf Stepped Oxide is disclosed. The inventive structure can apply additional freedom for better optimization and manufacturing capability by tuning thick oxide thickness to minimize influence of charge imbalance, trapped charges, etc. . . . . Furthermore, the fabrication method can be implemented more reliably with lower cost.