Abstract: A switching mode power supply with improved peak current control is disclosed. A varying reference signal is adopted to limit the peak current in the energy storage component. The varying reference signal is an exponential function of a time period when a power switch is ON, wherein the power switch is coupled to the energy storage component. The varying reference signal may be generated by a circuit comprising a RC circuit and one or several voltage sources.

Abstract: The present technology discloses a U-shape RESURF MOSFET device. Wherein the MOSFET device comprises a drain having a drain contact region and a drift region, a source, a body, a gate and a recessed-FOX structure. Wherein the recessed-FOX structure is between the gate and the drift region vertically and between the body and the drain contact region laterally, and wherein the recessed-FOX structure is configured to make the drift region into a U shape. The present technology further discloses the depth of the drift region is controlled by adjusting a layout width.

Abstract: A high voltage switching device and associated method of manufacturing, the high voltage switching device having a substrate, an epitaxial layer, a source region, a drain region, a drift region, a gate oxide, a filed oxide, a gate and a snake shaped poly.

Abstract: A switching charger having a control circuit configured to provide a control signal; a power stage turned ON and OFF by the control signal; an inductor coupled between the power stage and a load; and an output capacitor coupled in parallel with the load; a current sense circuit integrated to the control circuit to sense a current flowing through the power stage.

Abstract: A high voltage high side DMOS removing the N-buried layer from the DMOS bottom provides lower Ron*A at given breakdown voltage. The high voltage high side DMOS has a P-type substrate, an epitaxial layer, a field oxide, an N-type well region a gate oxide, a gate poly, a P-type base region, a deep P-type region, an N-type lightly doped well region, a first N-type highly doped region, a second N-type highly doped region and a P-type highly doped region.

Abstract: A switching charger having a control circuit configured to provide a control signal; a power stage turned ON and OFF by the control signal; an inductor coupled between the power stage and a load; and an output capacitor coupled in parallel with the load; wherein the control circuit limits a current flowing through the inductor in a hysteretic window, and wherein the hysteretic window is adjusted according to an ON time of the control signal.

Abstract: A voltage detecting circuit used with a switching converter. The switching converter having an energy storage component, a first power switch and a second switch. The voltage detecting circuit has a sample and hold circuit configured to sample and hold the voltage at the connection node of the energy storage component and the first power switch when the first power switch is OFF and the second power switch is ON; and an average circuit configured to average the sampled voltage during a switching period to generate a detecting signal in proportional to the output voltage of the switching converter.

Abstract: The present technology is directed generally to a semiconductor device. In one embodiment, the semiconductor device includes a first vertical transistor and a second vertical transistor, and the first vertical transistor is stacked on top of the second vertical transistor. The first vertical transistor is mounted on a lead frame with the source electrode of the first vertical transistor coupled to the lead frame. The second vertical transistor is stacked on the first vertical transistor with the source electrode of the second vertical transistor coupled to the drain electrode of the first vertical transistor.

Abstract: The present technology discloses a semiconductor die integrating a MOSFET device and a Schottky diode. The semiconductor die comprises a MOSFET area comprising the active region of MOSFET, a Schottky diode area comprising the active region of Schottky diode, and a termination area comprising termination structures. Wherein the Schottky diode area is placed between the MOSFET area and the termination area such that the Schottky diode area surrounds the MOSFET area.

Abstract: The embodiments of the present disclosure disclose a trench-gate MOSFET device and the method for making the trench-gate MOSFET device. The trench-gate MOSFET device comprises a curving dopant profile formed between the body region and the epitaxial layer so that the portion of the body region under the source metal contact has a smaller vertical thickness than the other portion of the body region. The trench-gate MOSFET device in accordance with the embodiments of the present disclosure has improved UIS capability compared with the traditional trench-gate MOSFET device.

Abstract: A drive and control circuit for motor system and the method thereof are disclosed. The motor system could be applied in a cooling device, wherein the motor system comprises a rotor, a coil and a bridge circuit. The drive and control circuit comprises a control unit, a state detecting circuit, a load determining circuit, and a startup setting circuit. The startup setting circuit makes the motor run with the maximum torque, thus to make the motor system start up easily and quickly. The load determining circuit detects the load of the motor system, thus to generate a load determining signal to determine the speed of the motor system. The control unit could be realized with few components so as to save the costs.

Abstract: An integrated circuit includes a junction field effect transistor (JFET) and a power metal oxide semiconductor field effect transistor (MOSFET) on a same substrate. The integrated circuit includes a drain sense terminal for sensing the drain of the power MOSFET through the JFET. The JFET protects a controller or other electrical circuit coupled to the drain sense terminal from high voltage that may be present on the drain of the power MOSFET. The JFET and the power MOSFET share a same drift region, which includes an epitaxial layer formed on the substrate. The integrated circuit may be packaged in a four terminal small outline integrated circuit (SOIC) package. The integrated circuit may be employed in a variety of applications including as an ideal diode.

Abstract: A SMPS having a switch; an output port coupled to a load, configured to provide a voltage feedback signal and a current feedback signal; an on-time generator, having an input end coupled to the current feedback signal, and having an output end providing a time signal indicating a time period; and a PWM generator, having a first input end coupled to the voltage feedback signal, a second input end coupled to the time signal, and an output end providing a PWM signal that is coupled to the control end of the switch, and wherein the PWM signal is configured to turn ON the switch when the voltage feedback signal is lower than a threshold voltage, and the PWM signal is configured to turn OFF the switch after the time period.

Abstract: A semiconductor device and a method for forming the semiconductor device wherein the semiconductor comprises: a trench MOSFET, formed on a semiconductor initial layer, comprising a well region, wherein the semiconductor initial layer has a first conductivity type and wherein the well region has a second conductivity type; an integrated Schottky diode next to the trench MOSFET, comprising a anode metal layer contacted to the semiconductor initial layer; a trench isolation structure, coupled between the trench MOSFET and integrated Schottky diode, configured to resist part of lateral diffusion from the well region; wherein the well region comprises an overgrowth part which laterally diffuses under the trench isolation structure and extends out of it.

Abstract: A constant ON-time converter is disclosed. The constant ON-time converter comprises a feedback circuit, a slope compensation circuit and a buffer circuit. The feedback signal comprises an output configured to provide a feedback signal indicating an output voltage of the constant ON-time converter. The slope compensation circuit comprises an output configured to provide a slope compensation signal. The buffer circuit is coupled between the output of the feedback circuit and the output of the slope compensation circuit to avoid the feedback signal and the output voltage of the constant ON-time converter is influenced by the slope compensation signal.

Abstract: A charger system with a digital interface circuit, wherein the digital interface circuit has an N-bit control register, wherein N is a positive integer no less than 2, and wherein the N-bit register has a primary state machine, at a first portion of addresses of the control register, configured to instruct operation statuses of a system management bus host; and a secondary state machine, at a second portion of addresses of the control register, configured to instruct a data bit of transmission of a corresponding control instruction under each of the operation statuses of the system management bus host.

Abstract: A JFET having a semiconductor substrate of a first doping type, an epitaxial layer of the first doping type located on the semiconductor substrate, a body region of a second doping type located in the epitaxial layer, a source region of the first doping type located in the epitaxial layer, a gate region of the second doping type located in the body region, and a shielding layer of the second doping type located in the epitaxial layer, wherein the semiconductor substrate is configured as a drain region, the shielding layer is in a conductive path formed between the source region and the drain region.

Abstract: A semiconductor device having an ESD protection structure and a method for forming the semiconductor device. The semiconductor device further includes a semiconductor transistor formed in an active cell area of a substrate. The ESD protection structure is formed atop a termination area of the substrate and is of solid closed shape. The ESD protection structure includes a central doped zone of a first conductivity type and a plurality of second-conductivity-type doped zones and first-conductivity-type doped zones alternately disposed surrounding the central doped zone. The central doped zone occupies substantially the entire portion of the ESD protection structure that is overlapped by a gate metal pad, and is electrically coupled to the gate metal pad. The outmost first-conductivity-type doped zone is electrically coupled to a source metal. The ESD protection structure features a reduced resistance and an improved current uniformity and provides enhanced ESD protection to the transistor.

Abstract: The present invention discloses a SMPS. The SMPS comprises an output port, configured to supply a load; a control signal generator, having an input and an output configured to provide a first control signal; a first switch configured to receive the first control signal and regulate the voltage at the output port; and a ramp signal generator, comprising an input and an output, wherein the input is configured to receive the control signal and the output is configured to provide a current signal simulating an output signal at the output port, and wherein the output of the ramp signal generator is further coupled to the input of the means for generating control signal.

Abstract: The present invention discloses a power supply. The power supply may comprise an input power terminal, a capacitor module, a first converter module and a second converter module. The first converter module may have a first terminal and a second terminal, wherein the first terminal is coupled to the input power terminal and the second terminal is coupled to the capacitor module. The second converter module may comprise an input and an output, wherein the input of the second converter module is coupled to the input power terminal, and the output of the second converter module is configured to supply a load.