Abstract: A method for finding the root causes of the failure of a faulty chip. The faulty chip comprises at least one defect. First, a type-searching step for the defect according to a defect size and a defect type to respectively predict a failure type of a predicted failure region relative to the defect is performed. Then, an influenced-range-searching step for the defect according to a defect location to respectively predict a failure range of a predicted failure region relative to the defect is performed. Finally, the predicted failure region of the defect and a real failure region which was electronically failed and been identified by the faulty chip are compared. If the predicted failure generated from the defect is located in the real failure region, the defect is interpreted to be one of the root causes of the failure of the faulty chip.

Abstract: The present invention provides a method of power IC inspection to inspect whether an electrically-failed portion of power ICs results from photo resist peeling before or during source implantation. First, the metal layers on the power ICs are removed by the conventional etching process, and then the dielectric layers on the power ICs are removed by the conventional etching process. Finally, the semiconductor substrate is put into an acid solution containing chromium (Cr), so that a close contour is shown at each of the power ICs whose photo resist didn't peel during photolithography process and after source implantation.

Abstract: The present invention is directed to an effective and relatively inexpensive way to measuring the depth of a well in a semiconductor device. In accordance with an aspect of the present invention, a method for measuring the depth of a well of a substrate comprises providing a substrate having a well therein and a cut through a depth of the well. The substrate is exposed to an etchant to reveal a discontinuity in a boundary at the depth of the well. The depth of the well is measured at the boundary by scanning electron microscopy (SEM) or other suitable techniques.

Abstract: Conductive material is deposited by ionized physical vapor deposition on an insulator, possibly to contact a conductive layer exposed by an opening in the insulator. At the beginning of the deposition, the wafer bias is low (possibly zero), to prevent the insulator re-sputtering by the ionized conductive material as this material is being deposited. The contact resistance is improved (reduced) as a result.

Abstract: Embodiments of the present invention are directed to an improved EEPROM (electrically erasable programmable read-only memory) in which the memory cells can be selectively erased. The EEPROM comprises a first memory cell having a first control gate and a first source, and a second memory cell having second control gate and a second source. If the first and second control gates are configured to receive a control gate voltage, the first source is configured to receive a first source voltage, and the second source is configured to receive a second source voltage different from the first source voltage so as to erase one of the first and second memory cells and to preserve another of the first and second memory cells.

Abstract: To form substrate isolation for a nonvolatile memory, floating gate polysilicon (410) is formed over a semiconductor substrate (110), then silicon nitride (130) is deposited, and then the nitride, the floating gate polysilicon and the substrate are etched to form isolation trenches (140). Dielectric (150) is formed in the trenches and over the silicon nitride. The dielectric thickness is relatively small so that the top surface (150T) of the dielectric over the trenches lies at all times below the top surface of silicon nitride. The dielectric deposition and polishing times are therefore reduced. Other embodiments are also provided.

Abstract: An alignment system and method for a wafer stage. A chopper is used. A wafer stage is disposed at one side of the chopper, while a detector is disposed at the other side of the chopper. The chopper is rotating with a constant angular frequency. The detector is to detect the wafer stage, while the wafer stage is covered by the blade of the chopper, the measured signal is zero, while the wafer stage is not covered by the bladed and is detected by the detector, a signal is obtained. Therefore, a duty cycle and a phase can be read from the detector. Thus, with a constant rotating angular frequency, an actual position of the measured object can be obtained to align the wafer stage.

Abstract: A method for fabricating deep-submicron DRAMs containing a deep trench capacitor with enlarged sidewall surface for improved storage capacitance. It includes the main steps of: (a) forming a silicon substrate having a (110) crystalline plane and a (111) crystalline plane; (b) forming a vertically extending deep trench into a crystalline silicon substrate; (c) filling the deep trench with a first dielectric material to form a first dielectric filler layer; (d) etching back the first dielectric filler layer to a first depth; (e) forming a dielectric collar from a second dielectric material which hangs on the sidewall of the deep trench extending from the opening of the trench to the first depth; (f) removing the first dielectric filler layer with a selective etching process; and (g) under a carefully timed exposure, using an isotropic etching solution which has high etching rate in the (110) plane and low etching rate in the (111) plane to form a roughened surface on the bottom surface of the deep trench.

Abstract: An upper cover plate for an air-tight chamber and a tool for removing the upper cover plate from the chamber are introduced. The upper cover plate integrates a chamber body to form the air-tight chamber, in which the chamber body further includes a top surface for air-tightly matching with a bottom surface of the upper cover plate. The upper cover plate further includes a plurality of thread holes engageable respectively with a plurality of the tools. The present invention is characterized on that at least one of the thread holes is formed as a through thread hole connecting to the bottom surface, and that the respective tool for engaging with the through thread hole includes a portion for penetrating the through thread hole and going beyond the bottom surface.

Abstract: The present invention relates to a monitor method for quality of metal Antireflection Coating (ARC) layer and, more particularly, to a fast and accurate monitor method for quality of metal ARC layer. By using of immersing a silicon wafer comprising an ARC layer into an acidic (such as a developer) or an alkalescent solution for about 200-300 seconds, according to the present invention, at weak points of the metal ARC layer there occur voids (defects) due to a Galvanic cell effect enhanced by these chemical solutions and then how many defects can be counted by a wafer defect inspector such as a KLA instrument so that quality of the metal ARC layer can be monitored by this defect number. Besides, Since the silicon wafer used as a sample for the wafer defect inspector simply comes from a production line, i.e. a developing process, rather than from other additional processing, said method allows for fast and accurately monitoring quality of the metal ARC layers.

Abstract: A few-particle-induced low-pressure TEOS process is disclosed. First, a lot of semiconductor substrates are arranged on a boat and transferred into a TEOS reactor. Silicon oxide films are then deposited on the semiconductor substrates by performing a low-pressure TEOS process. Before the substrates are sent out of the reactor, an annealing process is performed by injecting oxygen gas into the reactor to solidify the oxide films on the corners of the boat's flanges.

Abstract: Disclosed is a dual damascene process for a semiconductor device with two low dielectric constant layers in a stack thereof, in which a via hole and a trench connecting with the via hole are formed respectively in the dielectric layers and a conductor is filled in the via hole and the trench to connect with a conductive region below the via hole after a barrier layer between the via hole and the conductive region is removed. A liner is deposited on the sidewalls of the dielectric layers in the via hole and the trench before the removal of the barrier layer to prevent particles of the conductive region such as copper from sputtering up to the dielectric layers when removing the barrier layer. An etch-stop layer inserted between the dielectric layers is pulled back to be spaced from the via hole with a distance to improve the trench-to-via alignment.

Abstract: Embodiments of the present invention relate to an apparatus for spin drying substrates in a spin dryer tank. A spin dryer cover is movable between a closed position to close an opening of the spin dryer tank and an open position to open the spin dryer tank, and a cylinder is coupled with the spin dryer cover. The cylinder is movable in a first operation to move the spin dryer cover to the open position and movable in a second operation to move the spin dryer cover to the closed position. A system for sensing the position of the spin dryer cover comprises a cylinder sensor configured to sense the first operation and the second operation of the cylinder. A cover sensor is configured to sense the position of the spin dryer cover. A logic circuit is configured to output a cover opening signal indicating that the spin dryer cover is in the open position when the cylinder sensor senses the first operation of the cylinder and the cover sensor senses that the spin dryer cover is in the open position.

Abstract: The present invention is directed to an effective and relatively inexpensive way to measuring the depth of a well in a semiconductor device. In accordance with an aspect of the present invention, a method for measuring the depth of a well of a substrate comprises providing a substrate having a well therein and a cut through a depth of the well. The substrate is exposed to an etchant to reveal a discontinuity in a boundary at the depth of the well. The depth of the well is measured at the boundary by scanning electron microscopy (SEM) or other suitable techniques.

Abstract: A method and resulting integrated circuit device (100) such as a flash memory device and resulting cell. The method includes a step of providing a substrate (115), which has an active region overlying a thin layer of dielectric material (113). The method uses a step of forming a floating gate layer (107) overlying the thin layer of dielectric material (113), which is commonly termed a “tunnel oxide” layer, but is not limited to such a layer or material. The floating gate layer (107) has novel geometric features including slant edges (121), which extend to the dielectric material (123). The slant edges (121) create a smaller geometric area for the tunnel oxide region relative to the area between the floating gate layer and the control gate layer.

Abstract: A system and method for eliminating pulse width variations in digital delay lines partitions a delay line into two substantially identical blocks of delay inverters, inserting a first inverter between the two blocks and a second substantially identical inverter at the output of the second block. The requirement for matching device characteristics at the individual delay inverter level is eliminated and the only requirement is that the parasitic loading of the inverter between the blocks and the inverter on the output of the second block be the same. Consequently, the layout of the delay inverters in a single block may be made in the most efficient manner possible and the same identical layout can be used for the first and second blocks.

Abstract: The present invention provides an auxiliary tool for assembling a motor assembly to a wafer-deposition machine for supporting a wafer. The auxiliary tool facilitates easy and quick assembly of the motor assembly to the wafer-deposition machine. An aspect of the present invention is directed to an auxiliary tool for assembling a motor assembly to a wafer-deposition machine, wherein the motor assembly includes a plurality of first screw holes and the wafer-deposition machine includes a plurality of second screw holes corresponding to the first screw holes, respectively. The auxiliary tool comprises a plurality of locking members each having a substantially uniform dimension in a longitudinal direction and being configured to be inserted through one of the plurality of first screw holes of the motor assembly with a corresponding one of the plurality of second screw holes of the wafer-deposition machine to align the first screw hole with the corresponding second screw hole.

Abstract: A method for stabilizing a degas temperature of wafers in a degas chamber comprises (a) setting an electrical heater at an initial output power, (b) heating each wafer for a first period of time to keep the temperature of the wafer at a predetermined range by setting the electrical heater at a first output power equal to or higher than the initial output power, (c) heating the wafer for a second period of time to increase the temperature of the wafer to a predetermined value by raising the output power of the electrical heater to a second output power; and (d) heating the wafer for a third period of time by reducing the output power of the electrical heater to a third output power. The method lessens the “first wafer effect” and the “temperature-accumulated effect”. Therefore, the temperature of the wafers can be well controlled before a subsequent sputtering process.

Abstract: A method of polishing a wafer is disclosed. The wafer has formed thereon an oxide layer that has at least one via. A metal layer is formed on the oxide layer and in the via. The wafer is then polished against an outer portion of a polishing pad until the metal layer outside of the via has been removed. The outer portion has a first hardness. Next, the wafer is polished against an inner portion of the polishing pad. The inner portion of the polishing pad has a second hardness that is less than the first hardness.

Abstract: Embodiments of the present invention are directed to a metallization process for reducing the stress existing between the Al—Cu layer and the titanium nitride (TiN) layer, and solving the galvanic problem. The process does so by cooling the wafer in the vacuum apparatus where the metallization process is performed after formation of the Al—Cu layer and before the formation of the TiN layer. In accordance with an aspect of the present invention, a metallization process comprises placing a wafer in an Al—Cu sputtering chamber to form an Al—Cu layer on the wafer, and transferring the wafer to a titanium nitride sputtering chamber. An inert gas is introduced into the titanium nitride sputtering chamber to cool the wafer. A titanium nitride layer is formed on the Al—Cu layer of the wafer in the titanium nitride sputtering layer after cooling the wafer.