Abstract: A memory array and a method for preparing the memory are provided. The memory array includes a semiconductor substrate, an isolation structure and contact enhancement sidewall spacers. The semiconductor substrate has a trench defining laterally separate active areas formed of surface regions of the semiconductor substrate. Top surfaces of a first group of the active areas are recessed with respect to top surfaces of a second group of the active areas. The isolation structure is filled in the trench and in lateral contact with bottom portions of the active areas. The contact enhancement sidewall spacers laterally surround top portions of the active areas, respectively.

Abstract: The present application discloses a method for fabricating semiconductor device with a graphene-based element. The method includes providing a substrate; forming a stacked gate structure over the substrate; forming first spacers on sidewalls of the gate stack structure, wherein the first spacers comprise graphene; forming sacrificial spacers on sidewall of the first spacers; and forming second spacers on sidewall of the sacrificial spacers.

Abstract: The present application discloses a method for fabricating semiconductor device with a stress relief structure. The method includes providing a substrate, forming an intrinsically conductive pad above the substrate, and forming a stress relief structure above the substrate and distant from the intrinsically conductive pad.

Abstract: The present disclosure provides a method for controlling a data storage device. The method includes: storing a first data in a first area of a memory of the data storage device; storing a second data in a second area of the memory, wherein the second data is associated with the first; reading the first data and the second data via a first communication interface; and in response to the read first data and second data, generating a first output signal.

Abstract: The present disclosure relates to a method for preparing a semiconductor device including a conductive contact having a tapering profile and a method for preparing the semiconductor device. The method includes forming a conductive layer over a semiconductor substrate, and forming a dielectric layer covering the conductive layer. The method also includes etching the dielectric layer to form an opening exposing the conductive layer, and etching the dielectric layer to form a first recess and a second recess connecting to the opening. A depth of the opening is greater than a depth of the first recess and a depth of the second recess, and the first recess and the second recess have tapering profiles that taper toward the conductive layer. The method further includes forming a conductive contact over the conductive layer. The opening, the first recess and the second recess are filled by the conductive contact.

Abstract: The present application discloses a method for fabricating a semiconductor device with integrated decoupling alignment features. The method includes providing a first substrate; forming a plurality of first alignment marks on the first substrate and parallel to each other, wherein the first substrate and the plurality of first alignment marks together configure a first wafer; providing a second wafer comprising a plurality of second alignment marks parallel to each other; and bonding the second wafer onto the first wafer. The plurality of second alignment marks are arranged parallel to the plurality of first alignment marks and adjacent to the plurality of first alignment marks in a top-view perspective. The plurality of first alignment marks and the plurality of second alignment marks comprise a fluorescence material.

Abstract: A method for preparing the memory are provided. The method includes forming a trench at a front side of a semiconductor substrate, wherein the trench defines laterally separate active areas formed of surface regions of the semiconductor substrate; filling an isolation structure in the trench, wherein the isolation structure is filled to a height lower than top surfaces of the active areas; recessing a first group of the active areas from top surfaces of the first group of the active areas, while having top surfaces of a second group of the active areas covered; and forming contact enhancement sidewall spacers to laterally surround top portions of the active areas, respectively.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first stack structure positioned on a first substrate, a first impurity region and a second impurity region respectively positioned on opposing sides of the first stack structure and operatively associated with the first stack structure, a second stack structure positioned above the first stack structure with a middle insulation layer interposed therebetween, and a third impurity region positioned on one side of the second stack structure and electrically coupled to the second impurity region. The first stack structure includes a plurality of first semiconductor layers and a plurality of gate assemblies alternatively arranged. The plurality of gate assemblies includes a gate dielectric and a gate electrode. The second stack structure includes a plurality of second semiconductor layers and a plurality of capacitor sub-units alternatively arranged.

Abstract: This invention provides a temperature sensor circuit and its operation method. The temperature sensor circuit includes a temperature sensor, a temperature comparator, a plurality of temperature sensor enable clocks with different clock cycles and a clock selection circuit. The temperature sensor detects a temperature of an Integrated circuit and sending a signal indicative of the temperature. The temperature comparator executes a comparison between the temperature of the Integrated circuit and a predetermined temperature setting upon receiving the signal indicative of the temperature and sending an output according to the comparison. Upon receiving the output, the clock selection circuit provides one of the temperature sensor enable clocks according to the output to enable the temperature sensor. The temperature detection cycle of the temperature sensor is thus adjustable to save the temperature sensor power.

Abstract: A semiconductor structure including a semiconductor substrate, an active area, a transistor gate, a fuse gate, a first dielectric pattern, a second dielectric pattern and a plurality of metal lines is provided. The active area is disposed in the semiconductor substrate. The transistor gate has a first line segment and a second line segment extending across the active area in a first direction. The fuse gate located between the first line segment and the second line segment extends across the active area in the first direction. The first dielectric pattern is disposed between the active area and the transistor gate. The second dielectric pattern is disposed between the active area and the fuse gate. The metal lines disposed on two opposite sides of the transistor gate are electrically connected to the active device.

Abstract: An anti-fuse sensing device and an operation method thereof are provided. The anti-fuse sensing device includes an anti-fuse sensing circuit, a voltage generating circuit, and a power-on detection circuit. During a power-on transient period of the voltage generating circuit, the power-on detection circuit provides an initialization voltage to a control terminal of the anti-fuse sensing circuit to prevent a voltage level of the control terminal of the anti-fuse sensing circuit from being in an unknown state. After the power-on transient period ends, the voltage generating circuit provides a control voltage to the control terminal of the anti-fuse sensing circuit. The anti-fuse sensing circuit senses a resistance state of an anti-fuse based on the control voltage. During the period when the voltage generating circuit provides the control voltage, the power-on detection circuit stops providing the initialization voltage to the control terminal of the anti-fuse sensing circuit.

Abstract: A method for preparing a semiconductor device structure is provided. The method includes forming a first conductive layer over a semiconductor substrate, and forming a first dielectric layer over the first conductive layer. The first conductive layer includes copper. The method also includes etching the first dielectric layer to form a first opening exposing the first conductive layer, and forming a first lining layer and a first conductive plug in the first opening. The first lining layer includes manganese, the first conductive plug includes copper, and the first conductive plug is surrounded by the first lining layer. The method further includes forming a second conductive layer over the first dielectric layer, the first lining layer and the first conductive layer. The second conductive layer includes copper.

Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The method includes providing a substrate having a redistribution layer (RDL); disposing an etch stop layer over a RDL; patterning the dielectric layer and the etch stop layer; disposing a first seed layer over the etch stop layer and a portion of the dielectric layer that is exposed through the etch stop layer; disposing a second patterned photoresist over the first seed layer; disposing a conductive material over a portion of the first seed layer that is exposed through the second patterned photoresist; removing the second patterned photoresist; removing the etch stop layer; and removing a portion of the conductive material that protrudes from the dielectric layer to form a bonding pad adjacent to the conductive plug and surrounded by the dielectric layer.

Abstract: A method for forming a capacitor array includes depositing a first nitride layer, a first oxide layer, and a second nitride layer in sequence over first and second contacts on a substrate; etching the first nitride layer, the first oxide layer, and the second nitride layer to form first and second openings exposing the first and second contacts; conformally depositing a bottom electrode layer over the first and second nitride layers and the first oxide layer and on the first and second contacts; etching the second nitride layer and the first oxide layer to form a third opening having a bottom position higher than a top surface of the first nitride layer; removing the first oxide layer through the third opening; forming a capacitor dielectric layer over the bottom electrode layer; forming a top electrode layer over the capacitor dielectric layer.

Abstract: The present disclosure provides a method for preparing a semiconductor device structure with fine patterns at different levels. The method includes forming a hard mask material over a substrate; etching the hardmask material to form hard mask pillars; forming spacers over sidewall surfaces of the hard mask pillars; etching the hard mask pillars and the target material by using the spacers as a mask to integrally forming a plurality of target structures, a high-level recesses in one of the plurality of target structures and a low-level recess between two target structures; and integrally forming a high-level conductive pattern in the high-level conductive pattern and a low-level conductive pattern in the low-level recess.

Abstract: The present application provides a testing system. The testing system includes a chip socket and a probe. The chip socket includes a pedestal and a fastener. The pedestal is configured to accommodate a chip to be tested. The fastener includes a top body and a base body. The top body includes a probing window surrounded by a plurality of side walls, wherein the probing window has a first end at an outer surface of the top body and a second end at an inner surface of the top body, a first angle between a first side wall of the plurality of side walls and the outer surface is less than 90 degrees, and a first opening area at the first end of the probing window is larger than a second opening area at the second end of the probing window.

Abstract: A method of forming a capacitor structure includes following operations. A first electrode is formed. A hafnium-zirconium oxide (HZO) layer is formed over the first electrode under a first temperature. An interface dielectric layer is formed over the HZO layer under a second temperature greater than the first temperature. A second electrode is formed over the interface dielectric layer. The HZO layer and the interface dielectric layer are annealed.

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming an interconnect layer on a semiconductor component, wherein the interconnect layer contains at least one metal pad electrically coupled to the semiconductor component; depositing an insulating layer on the interconnect layer; depositing a bonding dielectric on the insulating layer; and forming a re-routing layer penetrating through the bonding dielectric and the insulating layer and contacting the interconnect layer.

Abstract: The present application discloses a semiconductor device with a carbon hard mask. The semiconductor device includes a substrate, conductive layers positioned on the substrate, a carbon hard mask layer positioned on the conductive layers, an insulating layer including a lower portion and an upper portion, and a conductive via positioned along the upper portion of the insulating layer and the carbon hard mask layer and positioned on one of the adjacent pair of the conductive layers. The lower portion is positioned along the carbon hard mask layer and positioned between an adjacent pair of the conductive layers, and the upper portion is positioned on the lower portion and on the carbon hard mask layer.

Abstract: A method for preparing a semiconductor device includes forming a ring structure over a semiconductor substrate, and etching the semiconductor substrate by using the ring structure as a mask to form an annular semiconductor fin. The method also includes epitaxially growing a first bottom source/drain structure within the annular semiconductor fin and a second bottom source/drain structure surrounding the annular semiconductor fin. The method further includes forming a first silicide layer over the first bottom source/drain structure and a second silicide layer over the second bottom source/drain structure. In addition, the method includes forming a first gate structure over the first silicide layer and a second gate structure over the second silicide layer, and epitaxially growing a top source/drain structure over the annular semiconductor fin.