Abstract: The present application discloses a method for fabricating a semiconductor device with capacitors having a shared electrode. The method includes providing a substrate, forming a first trench in the substrate, doping sidewalls and a bottom surface of the first trench to form a bottom conductive structure, forming a first insulating layer on the bottom conductive structure and in the first trench, forming a shared conductive layer on the first insulating layer, forming a second insulating layer on the shared conductive layer, forming a top conductive layer on the second insulating layer, and forming a connection structure electrically connecting the bottom conductive structure and the top conductive layer. The bottom conductive structure, the first insulating layer, and the shared conductive layer together configure a first capacitor unit. The shared conductive layer, the second insulating layer, and the top conductive layer together configure a second capacitor unit.

Abstract: The present disclosure provides a semiconductor device with an air gap for reducing parasitic capacitance between conductive features. The semiconductor device includes a first source/drain region and a second source/drain region disposed in a semiconductor substrate; a bit line structure disposed over and electrically connected to the first source/drain region; a capacitor contact disposed over and electrically connected to the second source/drain region; a first spacer structure sandwiched between the bit line structure and the capacitor contact, wherein the first spacer structure comprises an air gap; and a second spacer structure disposed over the first spacer structure, wherein the air gap is covered by the second spacer structure.

Abstract: A method for fabricating a semiconductor device includes providing a substrate; sequentially forming a layer of first conductive material, a layer of second conductive material, a layer of third conductive material, and an anti-reflective coating layer over the substrate; performing a plug etch process to turn the layer of first conductive material into a bottom conductive layer on the substrate, turn the layer of second conductive material into a middle conductive layer on the bottom conductive layer, and turn the layer of third conductive material into a top conductive layer on the middle conductive layer; selectively forming an insulating covering layer on a sidewall of the middle conductive layer, wherein the bottom conductive layer, the middle conductive layer, the top conductive layer, and the insulating covering layer together configure a plug structure; and forming a first dielectric layer on the substrate and surrounding the plug structure.

Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The method includes forming a bit line on a substrate, forming a first dielectric layer over the substrate and surrounding a lower portion of the bit line, forming a second dielectric layer over the bit line and the first dielectric layer, forming a contact over the second dielectric layer, wherein a height of the contact above the substrate is greater than a height of the first dielectric layer above the substrate, removing the first dielectric layer and the second dielectric layer, and forming a third dielectric layer conformally over the bit line, the substrate and the contact, thereby forming an air gap between the contact and the bit line.

Abstract: A receiver circuit that includes a pair of pre-stage amplifier circuits and a post-stage amplifier circuit is introduced. The pre-stage amplifier circuits are configured to receive an input signal and a reference voltage signal, output first pre-stage amplifying signals through a first connection node and a second connection node separately, and output second pre-stage amplifying signals through a third connection node and a fourth connection node separately. The post-stage amplifier circuit is configured to receive the first pre-stage amplifying signals and the second pre-stage amplifying signals from the pair of pre-stage amplifier circuits through the first connection node, the second connection node, the third connection node and the fourth connection node separately, and output a post amplifying signal according to the first pre-stage amplifying signals and the second pre-stage amplifying signals.

Abstract: A voltage generator and a voltage generating method are provided. The voltage generator includes at least one first charge pump circuit, at least one second charge pump circuit, an oscillator, a passing circuit, and a voltage detector. The first charge pump circuit is configured to receive a clock signal to generate a first pump voltage. The second charge pump circuit is configured to receive the clock signal to generate a first pump voltage. The oscillator is configured to provide the clock signal. The passing circuit is configured to receive the clock signal, a power-on detection signal and an external command. The voltage detector is configured to receive an operation voltage, and generate the power-on detection signal by detecting the operation voltage. The passing circuit determines whether to transmit the clock signal to the second charge pump circuit or not to activate or deactivate the second charge pump circuit.

Abstract: The present application provides a method for manufacturing a semiconductor package with air gaps for reducing capacitive coupling between conductive features. The method comprises: providing a first substrate with an integrated circuit; forming a first stack of insulating layers with first protruding portions on the integrated circuit; removing a topmost insulating layer in the first stack of insulating layers; forming through holes in the first stack to form a first semiconductor structure; providing a second substrate with an integrated circuit; forming a second stack of insulating layers with second protruding portions on the integrated circuit; forming a recess portion in the first stack to form a second semiconductor structure; and bonding the first semiconductor structure with the second semiconductor structure, with an air gap formed from the recess portion.

Abstract: The present disclosure provides a method for manufacturing a semiconductor device. The method includes providing a substrate comprising one or more isolation features defining active regions; forming at least one access transistor comprising a plurality of impurity regions, wherein the impurity regions are disposed in the substrate; depositing a dielectric layer to cover the access transistor; forming a first contact hole through the dielectric layer to expose the associated impurity region; forming a sacrificial liner in the first contact hole; removing a portion of the substrate exposed through the first contact hole and the sacrificial liner to form a second contact hole connected to the first contact hole; and forming a conductive feature in the first and second contact holes.

Abstract: A method of manufacturing a semiconductor, comprising: providing a stacked structure comprising a first oxide layer, a second oxide layer, and a metal layer stacked between the first oxide layer and the second oxide layer; forming a mask layer on the second oxide layer; introducing a gas mixture to the stacked structure, wherein the gas mixture comprises at least two hydrocarbon compounds and oxygen; and performing a pulsing plasma process to the stacked structure through the mask layer to pattern the second oxide layer and expose the metal layer through the patterned second oxide layer.

Abstract: The present disclosure relates to a method for preparing an electrical fuse (e-fuse) device. The method includes forming a mask layer over a semiconductor substrate, and etching the semiconductor substrate by using the mask layer as a mask to form a fuse link over a semiconductor base. The method also includes epitaxially growing a first bottom anode/cathode region and a second bottom anode/cathode region over the semiconductor base and adjacent to a bottom portion of the fuse link. The fuse link is between the first bottom anode/cathode region and the second anode/cathode region. The method further includes epitaxially growing a top anode/cathode region to replace the mask layer.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate, a semiconductor fin and a filled trench. The semiconductor fin extends upwards from the semiconductor substrate. The filled trench is formed in the semiconductor fin and includes a first sigma portion, a second sigma portion and a middle portion. The first sigma portion is partially filled by a semiconductor buffer region, and an unfilled part of the first sigma portion is filled by a doped semiconductor region grown on the semiconductor buffer region. The second sigma portion is filled by the semiconductor buffer region. The middle portion connects the first sigma portion to the second sigma portion, and the middle portion is filled by the semiconductor buffer region.

Abstract: A probe apparatus for testing a semiconductor device is provided. The testing device includes a socket having a cavity for accommodating a device under test (DUT), and a cover disposed on the socket. The socket includes a thermal conductive material. The cover includes a plate, a circuit board attached to the plate, and an opening penetrating the plate and the circuit board, exposing the cavity of the socket.

Abstract: A manufacturing method of a semiconductor device includes forming a bitline on a semiconductor structure comprising a conductive feature therein. A spacer is formed adjacent to a sidewall of the bitline, and the spacer has a dielectric contact in a range of about 2 to about 3. A sacrificial layer is formed over the semiconductor structure and covering the spacer. A portion of the sacrificial layer over the bitline is etched to form a first trench to expose a top surface of the bitline. A dielectric layer is formed in the first trench and over the bitline. After forming the dielectric layer, a remaining portion of the sacrificial layer is removed to form a second trench over the semiconductor structure and an outer sidewall of the first spacer is exposed. A contact is formed in the second trench and connected to the conductive feature of the semiconductor structure.

Abstract: A semiconductor device includes a substrate, a passing word line in the substrate, and a dielectric structure surrounding the passing word line. The dielectric structure has an enlargement portion at a bottom of the dielectric structure, and a maximum width of the enlargement portion of the dielectric structure is wider than a width of a top of the dielectric structure.

Abstract: A test circuitry structure includes a first pad, a second pad, a plurality of tested devices, and a plurality of switches. Each of the switches is coupled to each of the tested devices in series between the first pad and second pad. The switches are respectively triggered by a plurality of control signals to be turned on.

Abstract: A semiconductor device includes a conductive pattern formed over a semiconductor substrate, and an interconnect structure formed over the conductive pattern. The semiconductor device also includes a first passivation layer over the conductive pattern; a second passivation layer over the first passivation layer; an interconnect structure disposed over the conductive pattern and in the first passivation layer and the second passivation layer; and an interconnect liner disposed between the interconnect structure and the conductive pattern and surrounding the interconnect structure, wherein inner sidewall surfaces of the interconnect liner are in direct contact with the interconnect structure, and a maximum distance between outer sidewall surfaces of the interconnect liner is greater than a width of the conductive pattern.

Abstract: A method for overlay error correction includes generating a first overlay error based on a first overlay mark, wherein the first overlay error is indicative of a misalignment between a lower pattern and an upper pattern of the first overlay mark. The method also includes generating a second overlay error based on a second overlay mark, in response to an abnormal of the first overlay error is detected. The method further includes determining whether the abnormal of the first overlay error is caused by the misalignment between the lower pattern and the upper pattern depending on the second overlay error.

Abstract: A wafer-measuring apparatus and a wafer-transferring method of the wafer-measuring apparatus. The wafer-measuring apparatus includes a body, a wafer-measuring unit, a wafer storage, and a robot. The robot is disposed on the body and configured to move a wafer from a first wafer container to the wafer-measuring unit. The first wafer container is disposed on a load port area. The robot moves the wafer from the wafer-measuring unit to the wafer storage after the wafer-measuring unit measures the wafer.

Abstract: A data receiving circuit is provided. The data receiving circuit includes a data input circuit, a latch circuit, and an equalizer. The data input circuit is configured to receive an input signal, and the latch circuit is connected to the data input circuit and configured to output an output signal in response to the input signal. The equalizer includes a first transistor having a source connected to latch circuit; and a second transistor having a source connected to the latch circuit and a gate connected to a gate of the first transistor.

Abstract: The present disclosure provides a semiconductor structure for reducing capacitive coupling between adjacent conductive features. The semiconductor structure includes a base layer, a plurality of conductive lines, a plurality of dielectric pillars, and a sealing layer having a plurality of sealing caps. The conductive lines are disposed on the base layer. The dielectric pillars are disposed on the base layer and separated from the conductive layer. The sealing caps are disposed between the conductive lines and the dielectric pillars, wherein the sealing caps are in contact with the conductive lines and the dielectric pillars, and separated from the base layer.