Abstract: The present disclosure provides a method of manufacturing a semiconductor structure having an electrical contact. The method includes providing a semiconductor substrate; forming a dielectric structure over the semiconductor substrate, the dielectric structure having a trench; filling a polysilicon material in the trench of the dielectric structure; detecting the polysilicon material to determine a region of the polysilicon material having one or more defects formed therein; implanting the polysilicon material with a dopant material into the region; and annealing the polysilicon material to form a doped polysilicon contact.

Abstract: The present disclosure provides to a semiconductor memory device. The semiconductor memory device includes a substrate having a cell area and a peripheral area; and a first bit line structure disposed on and protruding from a surface of the cell area. The first bit line structure is sandwiched by a pair of air gaps and a barrier layer is conformally overlaying the air gaps adjacent to the sidewalls of the first bit line structure and the cell area. The first bit line structure has a sidewall and an ascending top portion, and a landing pad is disposed over the ascending top portion and the sidewalls of the first bit line structure. The landing pad has an inclined surface corresponding to the ascending top portion of the first bit line structure.

Abstract: The present application discloses a method for fabricating a semiconductor device with a flat surface. The method for fabricating a semiconductor device including providing a substrate, forming a gate structure on the substrate, and forming a plurality of word lines having top surfaces at a same vertical level as a top surface of the gate structure.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a pad structure positioned above the substrate and including a bottom portion and two side portions, wherein the bottom portion is positioned parallel to a top surface of the substrate, and the two side portions are positioned on two sides of the bottom portion and extending along a direction parallel to a normal of the top surface of the substrate; and an insulator film surrounding the pad structure. A top surface of the insulator film is at a vertical level greater than a vertical level of a top surface of the pad structure.

Abstract: A semiconductor device includes a first dielectric layer disposed over a semiconductor substrate, and a conductive contact penetrating through the first dielectric layer. The semiconductor device also includes a T-shaped landing pad structure disposed over and in direct contact with the conductive contact. The T-shaped landing pad structure includes a lower landing pad and an upper landing pad disposed over the lower landing pad, and a width of the upper landing pad is greater than a width of the lower landing pad. The semiconductor device further includes a capacitor disposed over and in direct contact with the T-shaped landing pad structure, and a second dielectric layer disposed over the first dielectric layer and surrounding the T-shaped landing pad structure and the capacitor.

Abstract: A semiconductor device includes a semiconductor substrate having a bonding pad, and a first dielectric layer disposed over the semiconductor substrate. A portion of the bonding pad is exposed by the first dielectric layer. The semiconductor device also includes a metal oxide layer disposed over the portion of the bonding pad, and a wire bond penetrating through the metal oxide layer to bond to the bonding pad. The portion of the bonding pad is entirely covered by the metal oxide layer and the wire bond.

Abstract: A method of forming a semiconductor structure includes following steps. A substrate is provided. The substrate has an active region, an isolation structure adjacent to the active region, and a contact on the active region. A dielectric stack is formed on the substrate. A poly layer is formed on the dielectric stack. The poly layer and the dielectric stack are etched to form an opening to expose the contact of the substrate. A conductive film is formed in the opening and an ALD oxide layer is deposited on a sidewall of the opening. In addition, a semiconductor structure is also disclosed herein.

Abstract: A probing device includes a probe station. The probe station has a platform having an opening and a plurality of column members supporting the platform. Each of the plurality of column members has one end connected with the platform and an opposite end connected with a moving part. The probing device also includes a manipulator on the platform and a socket configured to support a DUT. The manipulator has a probe. The moving part is configured to allow the probe station to be moved with respect to the DUT.

Abstract: The present disclosure provides a method of preparing active areas. The method includes the operations of: receiving a substrate having an oxide layer, a nitride layer, and a silicon layer thereon; forming a patterned photoresist layer on the silicon layer; depositing a mask layer to cover a contour of the patterned photoresist layer; coating a carbon layer on the mask layer; etching the carbon layer, the mask layer, and the silicon layer to expose a top surface of the nitride layer; forming a plurality of opens in the oxide layer to expose a top surface of the substrate; and growing an epitaxial layer from the top surface of the substrate in the plurality of opens to form the active areas.

Abstract: The present application provides a method of manufacturing a memory device having several word lines (WL) with reduced leakage. The method includes steps of providing a semiconductor substrate defined with an active area and including an isolation surrounding the active area; forming a first recess extending into the semiconductor substrate and across the active area; forming a first lining portion of a first insulating layer conformal to the first recess; disposing a first conductive material conformal to the first lining portion; forming a first conductive member surrounded by the first conductive material; disposing a second conductive material over the first conductive member to form a first conductive layer enclosing the first conductive member; and forming a first protruding portion of the first insulating layer above the first conductive layer and the first conductive member.

Abstract: A method includes forming a first conductive line and a second conductive respectively above a memory region and a peripheral region of a substrate. A capacitor is formed above the first conductive line. A bottom portion of a contact structure is formed above the second conductive line. A first dielectric layer is formed covering the capacitor and the bottom portion. First and second openings are formed in the first dielectric layer. The first opening is above the capacitor, and the second opening exposes the bottom portion. A middle portion of the contact structure and a gate material are respectively formed in the second opening and the first opening. A third opening is formed in the gate material to form a gate structure. A gate dielectric layer and a channel are formed in the third opening. A bit line is connected to the channel and the contact structure.

Abstract: The present application provides an overlay measuring apparatus, adapted to determine relative positions of two or more successive patterned layers of a device. The overlay measuring apparatus includes a stage and an imaging assembly. The device is placed on the stage. The imaging assembly includes a plurality of optical heads and a plurality of overlay marks assembled on the optical heads. The relative positions of the two or more successive patterned layers of the device are determined using light reflected from the device and passing through the overlay mark mounted on the respective optical head.

Abstract: The present disclosure provides a method of measuring a semiconductor device, including the following operations: obtaining a first image corresponding to a first layer in the semiconductor device; obtaining a second image corresponding to a second layer, below the first layer, in the semiconductor device, wherein the first layer includes at least one first structure and the second layer includes a plurality of second structures that are overlapped by the at least one first structure; generating a third image by combining the first image and the second image; and calculating an offset between the at least one first structure and the plurality of second structures based on the first image and the third image.

Abstract: A method of fabricating the semiconductor device includes forming a bit line structure over a substrate, forming a spacer structure on a sidewall of the bit line structure, partially removing an upper portion of the spacer structure to form a slope on the spacer structure slanting to the bit line structure, forming a landing pad material to cover the spacer structure and contact the slope, and removing at least a portion of the landing pad material to form a landing pad against the slope.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first chip including: a first inter-dielectric layer positioned on a first substrate; a plug structure positioned in the first inter-dielectric layer and electrically coupled to a functional unit of the first chip; a first redistribution layer positioned on the first inter-dielectric layer and distant from the plug structure; a first lower bonding pad positioned on the first redistribution layer; and a second lower bonding pad positioned on the plug structure; and a second chip positioned on the first chip and including: a first upper bonding pad positioned on the first lower bonding pad; a second upper bonding pad positioned on the second lower bonding pad; and a plurality of storage units electrically coupled to the first upper bonding pad and the second upper bonding pad.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a fin positioned on the substrate, a gate structure positioned on the fin, a pair of source/drain regions positioned on two sides of the fin, a dielectric layer positioned above the drain region and adjacent to the gate structure, and a storage conductive layer positioned on the dielectric layer. The drain region, the dielectric layer and the storage conductive layer form a storage structure.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first dielectric layer on a substrate; first/second upper short axis portions extending along a first direction, separated from each other, and on the first dielectric layer; a common source region in the substrate and adjacent to the first/second upper short axis portions; a first branch drain region in the substrate, adjacent to the first upper short axis portion, and opposite to the common source region; a second branch drain region in the substrate, adjacent to the second upper short axis portion, and opposite to the common source region; and a top electrode on the first dielectric layer and topographically above the first branch drain region and the second branch drain region. The top electrode, the first dielectric layer, and the first/second branch drain regions together configure a programmable unit.

Abstract: A method for fabricating a semiconductor device structure includes forming a first conductive layer over a semiconductor substrate, and forming a dielectric layer over the first conductive layer. The method also includes replacing a portion of the dielectric layer with an energy removable layer, and performing an etching process to form a first opening in the energy removable layer and a second opening in the dielectric layer. The first opening is in a pattern-dense region and the second opening is in a pattern-loose region. The method further includes depositing a lining layer over the energy removable layer and the dielectric layer. The lining layer entirely fills the first opening to form a first conductive plug, and the lining layer partially fills the second opening.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a bottom conductive layer positioned on the substrate; at least one bottom conductive protrusion positioned on the bottom conductive layer; an insulator layer positioned on the bottom conductive layer and the at least one bottom conductive protrusion; at least one bottom insulating protrusion protruding from the insulator layer towards the bottom conductive layer and adjacent to the at least one bottom conductive protrusion; and a top conductive layer positioned on the insulator layer. The bottom conductive layer, the at least one bottom conductive protrusion, the insulator layer, the at least one bottom insulating protrusion, and the top conductive layer together configure a capacitor structure.

Abstract: The present application provides a method for fabricating a semiconductor device including providing a first semiconductor die including a first substrate including a first substrate including a first region and a second region, a plurality of first through substrate vias in the first region, a first circuit layer on the first substrate, and a control circuit on the first region and in the first circuit layer; forming a plurality of through die vias vertically along the first circuit layer and the second region; providing a second semiconductor die including a plurality of second conductive pads substantially coplanar with a top surface of the second semiconductor die; providing a third semiconductor die including a plurality of third conductive pads substantially coplanar with a top surface of the third semiconductor die; flipping the second semiconductor die and bonding the second semiconductor die onto the first circuit layer.