Abstract: The present disclosure provides a method for preparing a semiconductor device with a copper-manganese liner. The method includes forming an opening structure in a first dielectric layer, wherein the opening structure has a first portion, a second portion and a third portion disposed between and physically connecting the first portion and the second portion; forming a lining material lining the first portion and the second portion of the opening structure and completely filling the third portion of the opening structure, wherein the lining material includes copper-manganese (CuMn); filling the first portion and the second portion of the opening structure with a conductive material after the lining material is formed; and performing a planarization process on the lining material and the conductive material.

Abstract: A method for preparing a semiconductor device structure includes forming a target layer over a semiconductor substrate, and forming a plurality of first energy-sensitive patterns over the target layer. The method also includes forming a lining layer conformally covering the first energy-sensitive patterns. A first opening is formed over the lining layer and between the first energy-sensitive patterns. The method further includes filling the first opening with a second energy-sensitive pattern, and performing an etching process to form a plurality of second openings and a third opening in the target layer, wherein the third opening is between the second openings, and the second openings and the third opening have different depths.

Abstract: The present disclosure provides a semiconductor structure having a test structure. The semiconductor structure includes a wafer and a test structure disposed on the wafer. The test structure includes a first device having a first source/drain layer and a first gate layer disposed above the first source/drain layer; a second device, having a second source/drain layer and a second gate layer disposed above the second source/drain layer, the second gate layer connected to the first gate layer; a third device, disposed adjacent to the first device and having a third source/drain layer. The first gate layer is disposed above the third source/drain layer, and the first gate layer is disposed along a first direction and the second gate layer is disposed along a second direction orthogonal to the first direction.

Abstract: A semiconductor device structure and method for manufacturing the same are provided. The semiconductor device structure includes a first metallization line, a second metallization line, a first isolation feature, a second isolation feature, a profile modifier, and a contact feature. The first metallization line and the second metallization line extend along a first direction. The first isolation feature and the second isolation feature are disposed between the first metallization line and the second metallization line. The first metallization line, the second metallization line, the first isolation feature and the second isolation feature define an aperture. The profile modifier is disposed within the aperture to modify a profile of the aperture in a plan view. The contact feature is disposed within the aperture.

Abstract: A test method includes: generating an error correction code according to a base data; dividing the base data into a plurality of base data sections; generating a plurality of candidate testing data according to the base data, wherein each of the candidate testing data has a plurality of testing data sections, and each of the testing data sections corresponds to each of the base data sections; and, performing a plurality of testing schemes. Each of the testing schemes includes: generating a plurality of write-in test data according to the plurality of candidate testing data, and writing the plurality of write-in test data with the error correction code into a tested device continuously; reading a plurality of mode register values of the tested device and a plurality of readout data from the tested device; and generating a test result according to the plurality of mode register value and the readout data.

Abstract: The present disclosure provides a package device. The package device includes a first integrated circuit chip, a second integrated circuit chip, a first input/output pin, and a first electrostatic discharge protection element. The first integrated circuit chip includes a first internal circuit and a first input/output pad disposed on the first integrated circuit chip and coupled to the first internal circuit. The second integrated circuit chip is stacked on the first integrated circuit chip. The second integrated circuit chip includes a second internal circuit and a second input/output pad disposed on the second integrated circuit chip and coupled to the second internal circuit. The first input/output pin is coupled to the first integrated circuit chip and the second integrated circuit chip. The first electrostatic discharge protection element is coupled between the first input/output pad and the first internal circuit.

Abstract: A method includes forming a semiconductor layer on a semiconductor substrate. The semiconductor layer is patterned to form a semiconductive structure. Each of widths of two ends of the semiconductive structure is wider than a width of a middle of the semiconductive structure. The semiconductive structure is doped to form a doped semiconductor structure. An isolation structure is formed to surround the doped semiconductor structure. A recessing process is performed such that two trenches are formed on the doped semiconductor structure, and first, second and third portions of an active region are formed on the semiconductor substrate. A first gate structure and a second gate structure are formed in the trenches such that the first portion and the third portion are partially spaced apart by the first gate structure, and the second portion and the third portion are partially spaced apart by the second gate structure.

Abstract: This invention provides a capacitor structure includes a U-shaped bottom electrode having a cap dielectric provided at its open end, a top electrode and a capacitor dielectric layer interposed between the bottom electrode and the top electrode to constitute an outer capacitor around a cylinder type solid inner capacitor, and the outer capacitor and the inner capacitor are divided by the cap dielectric. The cylinder type solid inner capacitor and the outer capacitor are fabricated separately so that the cylinder type solid inner capacitor may support its own weight to prevent its structure from being damaged during the fabrication of the capacitor.

Abstract: An electrical over stress protection device is provided. A detection circuit detects an input voltage from a pad, provides a first discharge path when the input voltage is higher than a preset voltage, and provides a turn-on voltage to a discharge protection circuit to control the discharge protection circuit to provide at least one second discharge path.

Abstract: The present disclosure provides a method for preparing a semiconductor device structure. The method includes forming a pad oxide layer over a semiconductor substrate; forming a pad nitride layer over the pad oxide layer; forming a shallow trench penetrating through the pad nitride layer and the pad oxide layer and extending into the semiconductor substrate; forming a first liner, a second liner and a third liner over sidewalls and a bottom surface of the semiconductor substrate in the shallow trench; filling a remaining portion of the shallow trench with a trench filling layer over the third liner; and planarizing the second liner, the third liner and the trench filling layer to expose the pad nitride layer. The first liner and the remaining portions of the second liner, the third liner and the trench filling layer collectively form a shallow trench isolation (STI) structure in an array area.

Abstract: The present application discloses method for fabricating a conductive feature and a method for fabricating a semiconductor device. The method includes providing a substrate; forming a recess in the substrate; conformally forming a first nucleation layer in the recess; performing a post-treatment to the first nucleation layer; and forming a first bulk layer on the first nucleation layer to fill the recess. The first nucleation layer and the first bulk layer configure the conductive feature. The first nucleation layer and the first bulk layer include tungsten. The post-treatment includes a borane-containing reducing agent.

Abstract: A fuse element, a semiconductor device, and a method for activating a backup unit are provided. The fuse element includes an active area, which includes a source region and a drain region beside the source region, a gate region disposed on the active area, and a shallow trench isolation (STI) structure surrounding the active area. In addition, the drain region includes a terminal configured to receive a stress voltage, such that a conductive path is established through the drain region to the source region.

Abstract: The disclosure provides a method of manufacturing a semiconductor device including bonding a second device wafer to a first device wafer, such that a first bonding interface including a dielectric-to-dielectric bonding interface and a metal-to-metal bonding interface is formed between the first device wafer and the second device wafer, wherein the second device wafer is electrically coupled to the first device wafer, and a function of the first device wafer and the second device wafer are the same kind of device wafer. A semiconductor device is also provided.

Abstract: The present application discloses a semiconductor device with a horizontally arranged capacitor. The semiconductor device includes a first palm portion positioned above a substrate; a second palm portion positioned above the substrate and opposite to the first palm portion; a first finger portion arranged substantially in parallel with a main surface of the substrate, positioned between the first palm portion and the second palm portion, and connecting to the first palm portion; a second finger portion arranged substantially in parallel with the first finger portion, positioned between the first palm portion and the second palm portion, and connecting to the second palm portion; a capacitor insulation layer positioned between the first finger portion and the second finger portion; a first spacer positioned between the first palm portion and second finger portion; and a second spacer positioned between the second palm portion and the first finger portion.

Abstract: The present disclosure provides to a method for preparing metal lines with a high aspect ratio comprising two photolithography stages. According to the design of the method of the present disclosure, first metal lines with high aspect ratio are formed in a dielectric layer, which provides a mechanical support to the first metal lines, thereby preventing the first metal lines from collapsing or deforming. Because of a significant reduction or elimination of collapse or deformation phenomenon in the semiconductor structure, a problem associated with short circuits due to direct contact between the semiconductor components can be mitigated, and reliability of the semiconductor structures can be enhanced. As a result, a yield of the semiconductor structure is increased.

Abstract: A method for preparing a semiconductor device is provided. The method includes forming a first dielectric layer over a semiconductor substrate, and forming a conductive contact penetrating through the first dielectric layer. The method also includes forming a lower landing pad over the conductive contact, and forming a second dielectric layer covering the lower landing pad. The method further includes etching the second dielectric layer to form a first opening exposing the lower landing pad, and forming an upper landing pad in the first opening. The lower landing pad and the upper landing pad form a T-shaped landing pad structure.

Abstract: A voltage regulator for providing a word line voltage is provided. The voltage regulator includes a voltage divider, a comparator, a boost circuit and a bypass transistor. The voltage divider is coupled between the word line voltage and a low reference voltage. The voltage divider includes resistive elements connected in series at intermediate nodes. The comparator provides an enable signal according to a divided voltage value on a divided intermediate node among the intermediate nodes. The boost circuit boosts the word line voltage in response to the enable signal. A source terminal of the bypass transistor is connected to a first intermediate node among the intermediate nodes. A drain terminal of the bypass transistor is connected to a second intermediate node among the intermediate nodes. The bypass transistor is turned-off in response to the control signal having an intermediate voltage value on the first intermediate node.

Abstract: An antifuse circuit includes a current generator and an antifuse sense unit. The current generator has at least one electronic device. The antifuse sense unit is electrically connected to the current generator, and the antifuse sense unit has at least one copied electronic device. An electronic device specification of the at least one electronic device of the antifuse sense unit is equal to an electronic device specification of the at least one copied electronic device of the current generator. The current generator supplies a current to the antifuse sense unit that senses an antifuse.

Abstract: A receiver circuit that includes a pair of pre-stage amplifier circuits and a post-stage amplifier circuit is introduced. A first pre-stage amplifier circuit includes a pair of first n-type transistors, and gate terminals of the first pair of the n-type transistors receive the input signal and the reference voltage signal, respectively. A second pre-stage amplifier circuit includes a pair of first p-type transistors, wherein gate terminals of the pair of the first p-type transistors receive the input signal and the reference voltage signal, respectively. The post-stage amplifier circuit outputs a post amplifying signal according to the first pre-stage amplifying signals and the second pre-stage amplifying signals. A memory device including the receiver circuit and an operation method thereof are also introduced.

Abstract: The present application provides a semiconductor package with air gaps for reducing capacitive coupling between conductive features and a method for manufacturing the semiconductor package. The semiconductor package includes a first semiconductor structure and a second semiconductor structure bonded with the first semiconductor structure. The first semiconductor structure has a first bonding surface. The second semiconductor structure has a second bonding surface partially in contact with the first bonding surface. A portion of the first bonding surface is separated from a portion of the second bonding surface, a space between the portions of the first and second bonding surfaces is sealed and forms an air gap in the semiconductor package.