Abstract: A digitizer system (DS) may include one or more input channels to receive sample data, and an acquisition state machine (ASM) to organize the sample data into one or more acquisition records according to events of interest, and generate framing information corresponding to the one or more acquisition records. The events of interest may be identified by a trigger circuit in the DS, and relayed to the ASM for organizing the sample data. The DS may further include a data interface capable of receiving the one or more acquisition records and the framing information, encoding the one or more acquisition records and the framing information into encoded data, and transmitting the encoded data to an expansion module. The expansion module may receive the encoded data, decode the encoded data, and recover the sample data from the decoded data according to the framing information and the one or more acquisition records.

Abstract: Apparatus and method for real-time scheduling. An apparatus includes first and second processing elements and a memory. The second processing element is configured to generate or modify a schedule of one or more tasks, thereby creating a new task schedule, and to write to a specified location in the memory to indicate that the new schedule has been created. The first processing element is configured to monitor for a write to the specified location in the memory and execute one or more tasks in accordance with the new schedule in response to detecting the write to the specified location. The first processing element may be configured to begin executing tasks based on detecting the write without invoking an interrupt service routine. The second processing element may store the new schedule in the memory.

Abstract: Customizing a target system. The target system may include a first device with a first programmable hardware element (PHE) and a second device with a second PHE. Synchronization modules may be provided for implementation on the first and second PHEs. The synchronization modules may provide a standard interface for interacting with other code. A user may specify user-created code for the first and second PHEs which utilizes the synchronization modules. The user-created code may interact with the synchronization modules using the standard interface. Accordingly, hardware descriptions may be generated for the first and second PHEs of the target system. Different modules may be used for different interconnects. Additionally, multiple synchronization modules may be used, e.g., dynamically, during operation of the target system.

Abstract: Communication devices and associated methods for reducing I/Q impairments in signals used by the communication devices are described. A transmitter device may perform filtering (or matrix multiplication) on digital I and Q signals to pre-correct them before converting them into analog I and Q signals. The pre-correction may pre-compensate for I/Q impairments which have not been introduced yet, but which will subsequently be introduced during digital-to-analog conversion, I/Q modulation, or other processing that occurs to produce a transmission signal from the original digital I and Q signals. A receiver device may receive a transmission signal, produce digital I and Q signals from the received signal, and perform filtering on the digital I and Q signals to correct I/Q impairments at a plurality of frequency offsets.

Abstract: Techniques for isochronous data transfer between different memory-mapped domains in a distributed system. A method includes configuring an isochronous engine with an isochronous period. The method further includes transferring data over a memory-mapped fabric from a first memory to a second memory during a specified portion of a cycle of the isochronous period. The first memory is comprised in a first device in a first memory-mapped domain of the memory-mapped fabric and the second memory is comprised in a second device in a second memory-mapped domain of the memory-mapped fabric. The method may further comprise translating one or more addresses related to the transferring. The memory-mapped fabric may be a PCI-Express fabric. The transferring may be performed by a DMA controller. A non-transparent bridge may separate the first and the second memory-mapped domains and may perform the translating.

Abstract: A low complexity system and method for operating a receiver in order to estimate an offset between the actual sample clock rate 1/TS? of a receiver and an intended sample clock rate 1/TS. The receiver captures samples of a received baseband signal at the rate 1/TS?, operates on the captured samples to generate an estimate for the clock rate offset, and fractionally resamples the captured samples using the clock rate offset. The resampled data represents an estimate of baseband symbols transmitted by the transmitter. The action of operating on the captured samples involves computing an error vector signal and then estimating the clock rate offset using the error vector signal. The error vector signal may be computed in different ways depending on whether or not carrier frequency offset and carrier phase offset are assumed to be present in the received baseband signal.

Abstract: Generating a hardware description for a programmable hardware element based on a graphical program including multiple models of computation. A graphical program may be received which includes a first portion having a first computational model and a second portion having a second computational model. A hardware description may be generated based on the graphical program. The hardware description may describe a hardware implementation of the graphical program. The hardware description may be configured to configure a programmable hardware element to implement functionality of the graphical program.

Abstract: Customizing a target system. The target system may include a first device with a first programmable hardware element (PHE) and a second device with a second PHE. Synchronization modules may be provided for implementation on the first and second PHEs. The synchronization modules may provide a standard interface for interacting with other code. A user may specify user-created code for the first and second PHEs which utilizes the synchronization modules. The user-created code may interact with the synchronization modules using the standard interface. Accordingly, hardware descriptions may be generated for the first and second PHEs of the target system. Different modules may be used for different interconnects. Additionally, multiple synchronization modules may be used, e.g., dynamically, during operation of the target system.

Abstract: Systems and methods for measuring transmitter and/or receiver I/Q impairments are disclosed, including iterative methods for measuring transmitter I/Q impairments using shared local oscillators, iterative methods for measuring transmitter I/Q impairments using intentionally-offset local oscillators, and methods for measuring receiver I/Q impairments. Also disclosed are methods for computing I/Q impairments from a sampled complex signal, methods for computing DC properties of a signal path between the transmitter and receiver, and methods for transforming I/Q impairments through a linear system.

Abstract: The present invention is related to a system (1) for determining a representation of a multi-tone signal (2) comprising a plurality of phase coherent tones, at least two of said phase coherent tones being modulated by a modulating signal, said system comprising an input (3) for applying the multi-tone signal (2), phase coherent mixing means (5) for demodulation in connection with data acquisition means (6) for digitization, said mixing means and data acquisition means arranged for being fed with the multi-tone signal and with a reference signal (8) comprising said phase coherent tones, each pair of phase coherent tones having a fixed phase difference, whereby the data acquisition means is arranged for being triggered by a trigger signal (4) for yielding a representation of said modulation signals with fixed delay, processing means (7) arranged for receiving digital signals output from the data acquisition means and for comparing phase information of a downconverted tone of the multi-tone signal after demodula

Abstract: A system and method for estimating carrier frequency offset ?f and carrier phase offset ?0 inherent in a received CPM signal. Samples of a continuous phase modulated (CPM) signal are received. A maximum of an objective function J is determined over a two-dimensional region parameterized by frequency offset v and phase offset w. The coordinates vmax and wmax of a maximizing point in the region represent estimates of the carrier frequency offset ?f and the carrier phase offset ?0. To evaluate the objective function J at a point (v,w), apply a frequency shift of amount ?v and a phase shift of amount ?w to the received samples to obtain modified samples, and perform Viterbi demodulation on the modified samples to obtain a winning path metric value at a final time. The winning path metric value is the objective function value J(v,w).

Abstract: A system and method for estimating carrier frequency offset ?f and carrier phase offset ?0 inherent in a received CPM signal. Samples of a continuous phase modulated (CPM) signal are received. A maximum of an objective function J is determined over a two-dimensional region parameterized by frequency offset v and phase offset w. The coordinates vmax and wmax of a maximizing point in the region represent estimates of the carrier frequency offset ?f and the carrier phase offset ?0. To evaluate the objective function J at a point (v,w), apply a frequency shift of amount ?v and a phase shift of amount ?w to the received samples to obtain modified samples, and perform Viterbi demodulation on the modified samples to obtain a winning path metric value at a final time. The winning path metric value is the objective function value J(v,w).

Abstract: System and method for specifying and implementing programs. A graphical program is created in a graphical specification and constraint language that allows specification of a model of computation and explicit declaration of constraints in response to user input. The graphical program includes a specified model of computation, a plurality of interconnected functional blocks that visually indicate functionality of the graphical program in accordance with the specified model of computation, and specifications or constraints for the graphical program or at least one of the functional blocks in the graphical program. The specified model of computation and specifications or constraints are useable to analyze the graphical program or generate a program or simulation.

Abstract: System and method for measuring distances in an image. An image is received that includes curves corresponding to one or more objects in the image. Multiple curves in a specified region of interest (ROI) in the image are detected, where the ROI has a specified direction. Each curve includes respective curve points. A convex hull is determined based on the respective curve points. One or more candidate antipodal point pairs of the convex hull are determined. A first point pair of the one or more antipodal point pairs is selected based on one or more specified constraints. A clamp angle corresponding to the first point pair is determined. A distance between the first point pair along a direction specified by the clamp angle is determined. The first point pair, the distance, and the clamp angle are stored. Calibration information may be applied at any point during the process.

Abstract: A user obtains a set of modules, inserts them into slots of a chassis, and interconnects the modules to form a modular instrument. A signal path extends through the modules. To support calibration of the signal path, a first of the modules (or the chassis or a calibration module) includes a calibration signal generator. A computer directs the first module to apply the calibration signal from the generator to the signal path, and measures the power (or amplitude) of the output of the signal path. The computer reads a factory-measured value A of the calibration signal amplitude from a memory of the first module (or the chassis or the calibration module). The value A and the measured output power of the signal path are used to determine a gain of the signal path. The system compensates for that gain when the signal path is used to measure live operational signals.

Abstract: System and method for performing program-related operations over a network via a web browser. A network connection is established between a server computer and a client computer over a network. A universal resource identifier (URI) is sent from the client computer to the server computer over the network, where the URI indicates a program, e.g., a graphical program (GP), or at least a portion of a graphical program interactive development environment (GPIDE), e.g., a graphical program editor, an execution engine, a static or dynamic analyzer, and/or compiler. The at least a portion of the GPIDE is received from the server computer over the network in response to the URI, and executed in a web browser of the client computer to perform some specified functionality with respect to the GP.

Abstract: The first and second outputs of a signal generation system are coupled to the first and second inputs of a signal digitizing system via respective electrical conductors. A controller directs the generation system to generate a first calibration signal, and the digitizing system responsively captures a first set of vector samples. The conductors are then reconfigured so they connect the first and second outputs of the generation system respectively to the second and first inputs of the digitization system. The controller then directs the generation system to generate a second calibration signal, and the digitizing system responsively captures a second set of vector samples. The controller or other processing agent computes gain and/or phase impairments using the first and second vector sample sets. Digital filter parameters may be computed based on the computed impairment(s), and used to correct the impairment(s) of the generation system and/or the digitizing system.

Abstract: Performing power quality and synchrophasor analysis on a resampled signal. A first signal may be initially received which corresponds to a power system. The first signal may have a plurality of cycles and may have a frequency that varies over time. One or more parameters may be determined from the first signal. Based on the one or more parameters, the first signal may be resampled to produce an even angle signal. Various power quality measurements may be performed on the even angle signal. Similarly, further processing may be performed to perform synchrophasor measurements, e.g., to determine phasor, frequency, and/or rate of frequency change for the first signal. In some embodiments, the resampling processing elements (e.g., circuitry, programmable hardware elements, processors and memories, etc.) may be shared between the two analyses.

Abstract: In some embodiments, a system may include a passive uniplanar single-balanced millimeter-wave mixer. In some embodiments, a three-port diode-tee IC forming a mixer core is coupled between an end of a slotline balun and a second coplanar balun. The operational bandwidth of a mixer structure is enhanced by optimizing the distance between the mixer diode-tee core and the back-short circuits. The frequency separation of LO and IF signals may be accomplished by means of stand-alone three-port filter-diplexer device. The system may allow wider than a frequency octave operational bandwidth for a frequency converter device all the way into millimeter wave frequencies at the same time as supporting the operational bandwidth for baseband IF signal over more than six frequency octaves. In some embodiments, the system may accomplish a 500 MHz to 34.5 GHz continuous IF bandwidth with RF signal sweeping from 33 GHz to 67 GHz and local oscillator at 67.5 GHz fixed frequency.

Abstract: Measurements, e.g. S-parameter measurements may be performed by obtaining a complex ratio of at least two signals, using a single signal-receiver while eliminating noise problems traditionally associated with single receiver systems. A Vector Signal Generator (VSG) may be used to generate the input stimulus (signal), making it possible to share the local oscillator (LO) signal of the VSG with a single vector receiver, such that the phase noise of the LO signal is common to both the VSG and the vector receiver. When the stimulus signal from the VSG is observed with the vector receiver, the LO phase noise is unobservable, resulting in a significant reduction of the phase noise in the measured signals in both the numerator and the denominator, which in turn leads to a significant reduction in the phase noise of the ratio while retaining the benefits of a simple, single receiver.