Abstract: System and method for hardware implemented accumulation of waveform data. A digitizer is provided that includes first and second memory banks. A first waveform is stored in chunks alternating between successive buffers in the first and second memory banks, and concurrently, the first and second chunks may be transferred to first and second FIFOs, respectively, which may be accumulated with respective first and second chunks of a second waveform into the first and second memory banks. This process may be repeated for respective successive pairs of the first and second waveforms, where the first and second memory banks and FIFOs are used in an alternating manner, and further, to accumulate additional waveforms, where previously stored (and accumulated) waveform data are accumulated chunkwise with successive additional waveform data, and where at least some of the accumulation is performed concurrently with waveform data transfers to and from the memory banks and FIFOs.

Abstract: Systems and methods for measuring transmitter and/or receiver I/Q impairments are disclosed, including iterative methods for measuring transmitter I/Q impairments using shared local oscillators, iterative methods for measuring transmitter I/Q impairments using intentionally-offset local oscillators, and methods for measuring receiver I/Q impairments. Also disclosed are methods for computing I/Q impairments from a sampled complex signal, methods for computing DC properties of a signal path between the transmitter and receiver, and methods for transforming I/Q impairments through a linear system.

Abstract: A method and system for scheduling a time critical task. The system may include a processing unit, a hardware assist scheduler, and a memory coupled to both the processing unit and the hardware assist scheduler. The method may include receiving timing information for executing the time critical task, the time critical task executing program instructions via a thread on a core of a processing unit and scheduling the time critical task based on the received timing information. The method may further include programming a lateness timer, waiting for a wakeup time to obtain and notifying the processing unit of the scheduling. Additionally, the method may include executing, on the core of the processing unit, the time critical task in accordance with the scheduling, monitoring the lateness timer, and asserting a thread execution interrupt in response to the lateness timer expiring, thereby suspending execution of the time critical task.

Abstract: In a real-time application, one or more computational tasks execute according to a time schedule and use input data from input devices and/or output data from output devices. One or more of the input devices or output devices may be unscheduled devices that attempt to access the peripheral bus at unscheduled times. Such unscheduled bus access can cause the time schedule to become comprised. Various methods for arbitrating access to the bus to better integrate the bus access with the time schedule followed by the application are described.

Abstract: A measurement apparatus is disclosed. The measurement apparatus includes a lid configured to be removably affixed to a microcircuit case. One or more penetrations through the lid allow insertion of a signal-conducting probe. The probe is removably affixed to the lid at the site of the penetration. The probe includes a central conductive pin. The central conductive pin transmits to a connection outside the case a radio-frequency signal inductively received from a source inside the case. The probe also includes a dielectric region radially surrounding a portion of the central conductive pin, and a grounded outer conductive housing radially surrounding the dielectric region and electrically isolated from the central conductive pin by the dielectric region.

Abstract: An improved measurement circuit includes a current transformer and an active feedback circuit operated as a negative resistance that matches the value of the winding resistance of the current transformer. An amplifier in the feedback circuit provides power to drive a secondary current through a sense resistor and the transformer winding resistance, reducing the most significant error source in a current transformer circuit by presenting a negative impedance to the current transformer. Combined with the positive resistance of the transformer's winding, the negative impedance results in a net burden of zero on the current transformer, which eliminates the need for the transformer having to provide power to drive the secondary current. This facilitates the use of smaller transformers while achieving reduced measurement errors. Thus, a single, compact measurement device may be used in a wide range of applications with high measurement performance.

Abstract: Customizing a target system. The target system may include a first device with a first programmable hardware element (PHE) and a second device with a second PHE. Synchronization modules may be provided for implementation on the first and second PHEs. The synchronization modules may provide a standard interface for interacting with other code. A user may specify user-created code for the first and second PHEs which utilizes the synchronization modules. The user-created code may interact with the synchronization modules using the standard interface. Accordingly, hardware descriptions may be generated for the first and second PHEs of the target system. Different modules may be used for different interconnects. Additionally, multiple synchronization modules may be used, e.g., dynamically, during operation of the target system.

Abstract: Customizing a target system. The target system may include a first device with a first programmable hardware element (PHE) and a second device with a second PHE. Synchronization modules may be provided for implementation on the first and second PHEs. The synchronization modules may provide a standard interface for interacting with other code. A user may specify user-created code for the first and second PHEs which utilizes the synchronization modules. The user-created code may interact with the synchronization modules using the standard interface. Accordingly, hardware descriptions may be generated for the first and second PHEs of the target system. Different modules may be used for different interconnects. Additionally, multiple synchronization modules may be used, e.g., dynamically, during operation of the target system.

Abstract: System and method for performing program-related operations over a network via a web browser. A network connection is established between a server computer and a client computer over a network. A universal resource identifier (URI) is sent from the client computer to the server computer over the network, where the URI indicates a program, e.g., a graphical program (GP), or at least a portion of a graphical program interactive development environment (GPIDE), e.g., a graphical program editor, an execution engine, a static or dynamic analyzer, and/or compiler. The at least a portion of the GPIDE is received from the server computer over the network in response to the URI, and executed in a web browser of the client computer to perform some specified functionality with respect to the GP.

Abstract: System and method for recording and displaying data associated with a program executing a program. Data associated with the program is displayed in a first instance of a graphical user interface (GUI) element. The data are saved one or more times during or after execution of the program in response to input, including saving information regarding the GUI element. The saved data are then displayed in a second instance of the GUI element in response to user input invoking display of the saved data, based on the saved information regarding the GUI element.

Abstract: A system and method for synchronizing a plurality of receivers. A tone from a signal generator is swept over a frequency band. A power splitter splits the tone into a plurality of resultant tones that are supplied to the respective receivers. For each receiver, a relative frequency response (including amplitude and phase responses) is measured between the receiver and a master receiver. A linear approximation to the phase response is computed. A digital filter is custom designed for the receiver to compensate for non-uniformity of the amplitude response and for deviations of the phase from the linear approximation. After applying the digital filter, further adjustments are made to remove the time delay corresponding to the linear approximation, e.g., by appropriately configuring a fractional resampler, by adjusting a numerically-controlled oscillator, and/or, by adjusting sample clock phase.

Abstract: A source-measure unit (SMU) may be implemented with respective digital control loops for output voltage and output current. The output voltage and output current may be measured with dedicated ADCs (analog-to-digital converters). The readings obtained by the ADCs may be compared to a setpoint, which may be set in a digital loop controller. The digital loop controller may be used to produce an output to drive a DAC (digital-to-analog converter) until the output voltage and/or output current and/or a function thereof reach the respective desired levels. The digital loop controller may implement respective integrating functions for the respective digital control loops, and may also implement a compensation function featuring pole-zero pairs to stabilize the respective current/voltage outputs. Coefficients of the compensation function may be calculated based on user programmable parameters corresponding to the gain bandwidth product, compensation frequency, and ratio of the added pole-zero frequencies.

Abstract: System and method for computing QR matrix decomposition and inverse matrix R?1. A circuit is configured to implement a QR decomposition of a matrix A into two matrices Q and R using a Modified Gram Schmidt (MGS) process. The circuit includes a specified portion dedicated to computing matrix Q. Matrix Q is computed via the specified portion based on first inputs using the MGS process, where the first inputs include the matrix A and possibly a scaling factor ?. The identity matrix may be scaled by the scaling factor ?, thereby generating scaled identity matrix ?I. Scaled matrix ?R?1 (or unscaled R?1) may be computed via the specified portion based on second inputs provided to the portion using the MGS process, where the second inputs include the (possibly scaled) identity matrix. If scaled, the scaled matrix ?R?1 may be unscaled, thereby computing matrix R?1. Matrix R?1 is stored and/or output.

Abstract: Customizing a test instrument. A plurality of pairs of code modules may be provided. Each pair of code modules may include a first code module having program instructions for execution by a processor of the test instrument and a second code module for implementation on a programmable hardware element of the test instrument. For each pair of code modules, the first code module and the second code module may collectively implement a function in the test instrument. User input may be received specifying modification of a second code module of at least one of the plurality of pairs of code modules. Accordingly, a hardware description may be generated for the programmable hardware element of the test instrument based on the modified second code module.

Abstract: A motion control interface device includes an FPGA configured to implement a step generation algorithm that generates step control signals for a motion device. The signals are not determined based directly on time, but instead are determined from the position of the motion device. More particularly, the step generation algorithm operates to keep track of a position fraction based on the position. The position fraction is incremented (or decremented) at each clock tick of the FPGA. The algorithm generates rising edge signals when the position fraction crosses a particular threshold value, referred to as the rising edge threshold value. Similarly, the algorithm signals direction changes when the position fraction crosses a threshold referred to as the direction change threshold value.

Abstract: Magnetic linear actuator (MLA) and use. The MLA includes a driver portion with motor and rotating mount with a first magnet (M1) having poles aligned in a plane, and an actuator portion, having a frame with a second magnet (M2) proximate to a first end of the frame with a specified pole facing the frame's center, and a third magnet (M3) proximate to a second end of the frame with the specified pole facing the frame's center. The frame holds M2 and M3 collinear with M1, in the plane, and on opposite sides of the M1, and is constrained to move along an axis collinear with M1, M2, and M3. During operation, the motor rotates M1 through a first orientation where M1 attracts M2 and repels M3, then a second orientation where M1 repels M2 and attracts M3, in response to which the frame moves back and forth, e.g., reciprocates.

Abstract: A method and system configured to: (a) display a first diagram including a first icon in response to input selecting the first icon; (b) associate the first icon with a first hardware device in response to input selecting the first hardware device from a set of hardware devices; (c) associate the first icon with a set of physical channels of the first hardware device in response to user input selecting the physical channels; and (d) perform the following operations one or more times: receive user input selecting a resource from a set of available resources including resources on the first hardware device; update the first diagram to include a graphical representation of the selected resource; receive user input to the first diagram specifying configuration information for the selected resource; and store the configuration information; (e) display a dataflow node indicating a transfer operation to be performed.

Abstract: Systems and methods for measuring transmitter and/or receiver I/Q impairments are disclosed, including iterative methods for measuring transmitter I/Q impairments using shared local oscillators, iterative methods for measuring transmitter I/Q impairments using intentionally-offset local oscillators, and methods for measuring receiver I/Q impairments. Also disclosed are methods for computing I/Q impairments from a sampled complex signal, methods for computing DC properties of a signal path between the transmitter and receiver, and methods for transforming I/Q impairments through a linear system.

Abstract: Performing spectral analysis may include, for each of multiple acquisitions: a receiving a plurality of time-domain samples, cross-power spectrum analyzing first and second portions of the plurality of samples resulting in cross-power spectra, and accumulating a vector sum of the cross-power spectra including any cross-power spectra from previous acquisitions. Performing spectral analysis may also include calculating a vector average based on the accumulated vector sum and quantity of acquisitions. Performing spectral analysis may also include displaying the magnitude of the vector average.

Abstract: A system and method for reserving resources of a host computer for use by an external device configured to be coupled to an expansion bus of the host computer are described. The host computer may be configured to execute device resource software that operates at a startup of the host computer to reserve one or more resources for the external device. The external device may not be available during the startup of the host computer, e.g., because the external device is not powered on or is not physically connected to the host computer. The device resource software may subsequently detect that the external device becomes available after the startup of the host computer. In response, the device resource software may enable the external device to use the one or more resources that were previously reserved at the startup of the host computer.