Abstract: Systems and methods for scheduling data egress using a time-sensitive (TS) network switch. The TS network switch may include a functional unit, a plurality of ports, and a plurality of queues. Each port may be associated with a set of network addresses for TS packets and may be configured with a set of egress periods. Each queue may be associated with a TS packet type and a port. The functional unit may be configured to receive TS packets asynchronously from a network node via a first port, determine a second port for egressing a TS packet, determine an egress period for egressing the TS packet, determine that the TS packet cannot currently be egressed from the second port, queue the TS packet in a first queue, where the first queue is associated with the second port, and egress the TS packet in the respective time window from the second port.

Abstract: A signal processing system implemented on a Field Programmable Gate Array (FPGA) operates according to a low frequency K-Clock to sample Optical Coherence Topography (OCT) signals, as opposed to relying on a high frequency K-Clock to obtain the same information. A resampler is used to resample the OCT signal uniformly in the optical frequency domain. The resampling may be performed by extracting instantaneous phase information from a low-frequency digitized K-Clock signal, unwrapping the extracted phase information, multiplying the unwrapped extracted phase information with an interpolation factor to obtain recalculated phase information, determining one or more integer crossing points corresponding to the recalculated phase information, and interpolating one or more values of the OCT signal based on the one or more integer crossing points. The integer crossing points may represent points in phase divisible by 360 degrees, within the range of points in phase defined by the recalculated phase information.

Abstract: A power converter may have an input stage that includes a pair of transformer coils, switching circuitry to energize the pair of transformer coils according to an input supply voltage provided by an input source, and a limiting circuit coupled between the pair of transformer coils to cause the input stage to stop drawing current from the input source once the amount of charge drawn from the input source reaches a specific value. An output stage of the power converter may receive energy from the pair of transformer coils, and convert the received energy into an output supply voltage. The pair of transformer coils may continue providing energy stored in a leakage inductance of the pair of transformer coils to the output stage for at least a period of time, once the limiting circuit has caused the input stage to stop drawing current from the input supply.

Abstract: System and method implementing an integrated interface for multiple instruments for signal analysis, including two or more virtual instruments. The method includes a) receiving user input specifying an operation implementing at least a portion of a signal analysis function; b) performing the operation utilizing at least one of the instruments to perform the operation; c) displaying an icon comprising a graphical representation of the operation in response to the specifying; d) storing information specifying the operation; and repeating a)-d) multiple times to specify the function, thereby producing stored information representing the operations in the function, and after which multiple icons are displayed representing the operations and visually indicating the function. The operations in the function include 1) generating signals displayed in a graph, and/or 2) modifying one or more signals displayed in the graph.

Abstract: A method and system is presented which provides a TDM framework for managing self-describing measurement data. The TDM framework provides applications with a central platform for accessing measurement data across an entire enterprise system. By means of individual plug-ins, which may be specific to a given data file format, meta-data for each data store in the enterprise may be indexed in a unified manner. The unified indexing, in turn, provides the ability to browse and query the indexed measurement data without requiring the opening or reading from a source data file.

Abstract: A current measurement connector may include a first part and a second part. Each part may include a mount and a joint. The first and second part may be joined via the respective joints through a current transformer interposed between the first and second parts. The respective mounts may be configured to receive a current from a current source and pass the received current through the current transformer via the first and second parts inducing a current in the current transformer. The induced current may be useable to measure the current from the current source. Methods for fabricating the current measurement connector may include die casting the first and second parts and press fitting the first and second parts at the respective joints through the current transformer. Methods for use may include withstanding a fault current pulse and dissipating heat associated with the pulse via the first and second parts.

Abstract: System and method for validating a program under a specified model of computation. The model of computation may be related to the synchronous statechart model of computation. A program may be received that specifies a plurality of operations using a variable within a logical tick such that the variable has multiple values within the logical tick. The program may be statically analyzed according to a specified model of computation that specifies program execution based on logical ticks, which may include determining that the program has deterministic semantics that specify deterministic results for each logical tick during execution of the program, including specifying deterministic results of the plurality of operations performed within the logical tick. The program may be validated in accordance with the specified model of computation in response to the determining. Such techniques may allow validation of a larger set of programs than conventional models while maintaining deterministic results.

Abstract: A hybrid diplexer combining planar transmission line(s) and a waveguide is disclosed. In one embodiment, a diplexer includes first, second, and third ports. The diplexer also includes a first signal path and a second signal path. The first signal path may be used to convey lower frequencies, and may be implemented using planar transmission lines. The second signal path may be used to convey higher frequencies, and may be implemented, at least in part, using a waveguide. The first signal path may be coupled between the first port and the second port, while the second signal path may be coupled between the first port and the third port. In one embodiment, the first signal path may implement a low-pass filter, while the second signal path may implement a high-pass filter.

Abstract: In one embodiment, a high frequency module may include a substrate. The substrate may include a first surface and a second surface substantially opposite of the first surface. The high frequency module may include a component coupled to the second surface. A direct current may be provided to the component using the substrate. The high frequency module may include a core coupled to the second surface of the substrate. In some embodiments, the core may include at least one opening extending through the core. The component may be positioned in at least one of the openings. In some embodiments, the high frequency module may include a cover coupled to the core. The component may be positioned in at least one of the openings between the substrate and the cover.

Abstract: Systems and methods for mapping an iterative time-based data acquisition (DAQ) operation to an isochronous data transfer channel of a network. A time-sensitive buffer (TSB) associated with the isochronous data transfer channel of the network may be configured. A data rate clock may and a local buffer may be configured. A functional unit may be configured to initiate continuous performance of the iterative time-based DAQ operation, transfer data to the local buffer, initiate transfer of the data between the local buffer and the TSB at a configured start time, and repeat the transferring and initiating transfer in an iterative manner, thereby transferring data between the local buffer and the TSB. The TSB may be configured to communicate data over the isochronous data transfer channel of the network, thereby mapping the iterative time-based DAQ operation to the isochronous data transfer channel of the network.

Abstract: A selectively transparent bridge facilitates a PCI device presenting itself to the host as a PCI-to-PCI bridge but selectively hiding and isolating hardware from the host bus. PCI configuration may be achieved through the standard PCI Express configuration mechanisms, but instead of configuring devices directly, a configuration processor in the selectively transparent bridge may intercept the configuration packets from the host, and create a virtual configuration to alter how the bus topology appears to the host. Devices are selectively hidden and managed by the configuration processor, resulting in simplified complexity and bus depth. Since the selectively transparent bridge appears to the host as a transparent bridge, no special drivers or resource preallocations are required, although the selectively transparent bridge fully supports special drivers and/or resource preallocations. Devices located/connected downstream of the bridge may therefore function with unmodified drivers.

Abstract: System and method for developing a motion application. A motion manager component implementing a supervisory control function and at least one trajectory generation algorithm is stored on a motion controller. A first application programming interface (API) for interfacing the motion manager component to a user developed motion control application is displayed. A second API for interfacing the motion manager component to a user developed communication interface component is displayed. A user application executable for sequencing motion operations in the motion system is created using the first API is created in response to user input. A first communication interface component is created using the second API in response to user input, where the communication interface component is operable to interface with the motion manager component using the second API, and where the user developed communication interface component is executable to communicate with a motion element, e.g., a drive or simulation.

Abstract: System and method for configuring a system of heterogeneous hardware components, including at least one: programmable hardware element (PHE), digital signal processor (DSP) core, and programmable communication element (PCE). A program, e.g., a graphical program (GP), which includes floating point math functionality and which is targeted for distributed deployment on the system is created. Respective portions of the program for deployment to respective ones of the hardware components are automatically determined. Program code implementing communication functionality between the at least one PHE and the at least one DSP core and targeted for deployment to the at least one PCE is automatically generated. At least one hardware configuration program (HCP) is generated from the program and the code, including compiling the respective portions of the program and the program code for deployment to respective hardware components. The HCP is deployable to the system for concurrent execution of the program.

Abstract: Method and memory medium for generating a web service. A plurality of graphical data flow programs may be provided, and user input selecting one or more of plurality of graphical data flow programs for inclusion in a web service may be received, The web service may be generated based on the one or more graphical data flow programs. Each graphical data flow program may implement a respective web method, where each web method may implement or request a respective action. The web service may be deployable to a server for hosting, where the web service is invocable over a network to perform the corresponding one or more web methods.

Abstract: System and method for computing QR matrix decomposition and inverse matrix R?1. A circuit is configured to implement a QR decomposition of a matrix A into two matrices Q and R using a Modified Gram Schmidt (MGS) process. The circuit includes a specified portion dedicated to computing matrix Q. Matrix Q is computed via the specified portion based on first inputs using the MGS process, where the first inputs include the matrix A and possibly a scaling factor ?. The identity matrix may be scaled by the scaling factor ?, thereby generating scaled identity matrix ?I. Scaled matrix ?R?1 (or unscaled R?1) may be computed via the specified portion based on second inputs provided to the portion using the MGS process, where the second inputs include the (possibly scaled) identity matrix. If scaled, the scaled matrix ?R?1 may be unscaled, thereby computing matrix R?1. Matrix R?1 is stored and/or output.

Abstract: System and method for configuring a measurement device. An initial configuration of a measurement device may be stored on a storage medium. In response to a change in the configuration of the measurement device, information indicating the change in the configuration may be stored on the storage medium, where the change in the configuration results in a modified configuration. Storing the information indicating the change in the configuration may be repeated one or more times for respective changes. The stored initial configuration and the stored information indicating changes in the configuration may comprise a history of configuration changes for the measurement device which may be useable to perform one or more of: generating a report regarding the measurement device, displaying a history of changes in the configuration of the measurement device, or reverting the measurement device to a previous configuration.

Abstract: Measurements, e.g. S-parameter measurements may be performed by obtaining a complex ratio of at least two signals, using a single signal-receiver while eliminating noise problems traditionally associated with single receiver systems. A Vector Signal Generator (VSG) may be used to generate the input stimulus (signal), making it possible to share the local oscillator (LO) signal of the VSG with a single vector receiver, such that the phase noise of the LO signal is common to both the VSG and the vector receiver. When the stimulus signal from the VSG is observed with the vector receiver, the LO phase noise is unobservable, resulting in a significant reduction of the phase noise in the measured signals in both the numerator and the denominator, which in turn leads to a significant reduction in the phase noise of the ratio while retaining the benefits of a simple, single receiver.

Abstract: Performing power quality and synchrophasor analysis on a resampled signal. A first signal may be initially received which corresponds to a power system. The first signal may have a plurality of cycles and may have a frequency that varies over time. One or more parameters may be determined from the first signal. Based on the one or more parameters, the first signal may be resampled to produce an even angle signal. Various power quality measurements may be performed on the even angle signal. Similarly, further processing may be performed to perform synchrophasor measurements, e.g., to determine phasor, frequency, and/or rate of frequency change for the first signal. In some embodiments, the resampling processing elements (e.g., circuitry, programmable hardware elements, processors and memories, etc.) may be shared between the two analysis.

Abstract: A system and method for enabling a graphical program to natively access an external memory buffer are disclosed. The graphical program may execute within a graphical program execution environment, and the external memory buffer may be allocated by another program that executes externally from the graphical program and the graphical program execution environment. The graphical program may be executed concurrently with a producer program that stores data in the memory buffer, and/or with a consumer program that reads and uses the data from the memory buffer. The memory buffer may be located within a region of memory allocated by the producer program, by the consumer program, or by another program that executes externally from the graphical program and the graphical program execution environment, such as a memory manager program.

Abstract: System and method for convergence analysis. One or more state variables of a first program may be determined based on dependencies of variables in a first program. A second program corresponding to the first program is created based on the state variables and their dependencies, and executed multiple times. Each execution may include recording values of the state variables, determining an execution count, comparing the values to corresponding values from previous executions of the second program, and terminating the executing in response to the values matching corresponding values from at least one previous execution of the second program. A convergence property for the first program is determined based on the execution count, and indicating a number of executions of the first program required to generate all possible values of the one or more variables. The convergence property is stored, and may be useable to optimize the first program.