Abstract: A control circuit for use in a battery charger circuit that includes a switching voltage regulator, with the control circuit having a constant current charging mode and a constant voltage charging mode. A switcher controller is provided which configured to control a state of a top side switching transistor and a low side transistor of the switching voltage regulator in response to at least one error signal. A power path transistor switch is disposed intermediate an output of the switching voltage regulator and a first node for receiving a first terminal of a battery to be charged.

Abstract: A battery charger circuit having a regulator controller configured to control the switching transistors of a switching voltage regulator. A power path switch is disposed intermediate an output of the switching voltage regulator and a terminal of a battery to be charged, with the power path switch including at least two transistor segments having common respective drain electrodes, common respective source electrodes and separate respective gate electrodes. A power path switch controller operates to sequentially turn ON the at least two transistor segments of the power path switch, preferably in the order of a decreasing ON resistance.

Abstract: The present inventions relate to methods and arrangements for using a thin foil to form electrical interconnects in an integrated circuit package. In one embodiment, a foil carrier structure is formed by ultrasonically bonding portions of a conductive foil to a metallic carrier. The bonded portions define panels in the foil carrier structure. In some embodiments, the foil carrier structure is cut to form multiple isolated panels that are sealed along their peripheries. Each isolated panel may be approximately the size of a conventional leadframe strip or panel. As a result, existing packaging equipment may be used to add dice, bonding wires and molding material to the panel. The ultrasonic welding helps prevent unwanted substances from penetrating the foil carrier structure during such processing steps. After the carrier portion of the molded foil carrier structure is removed, the structure is singulated into integrated circuit packages.

Abstract: A plurality of mobile communication devices for performing one or more locally collaborative operations. In one embodiment, one of the mobile communication devices provides a first local energy emission and, related thereto, a local wireless transmission signal, while another of the mobile communication devices responds to the local wireless transmission signal by providing a second local energy emission related to the first local energy emission. In another embodiment, one of the mobile communication devices receives a local stimulus, exclusive of vocal energy emitted by a user, and in response thereto provides a local wireless transmission signal, while another of the mobile communication devices responds to the local wireless transmission signal by providing a local energy emission related to the local stimulus.

Abstract: A system includes a master device and multiple slave devices. The system also includes multiple bus interfaces forming a communication bus that couples the master and slave devices. Each bus interface includes a primary interface unit configured to communicate over first and second buses, where the first and second buses form a portion of the communication bus. Each bus interface also includes a secondary interface unit configured to communicate with the primary interface unit and to communicate with one of the slave devices over a third bus. Each bus interface further includes an isolator configured to electrically isolate the primary interface unit and the secondary interface unit. The primary interface unit is configured to receive multiple commands over the first bus, execute a first subset of commands, transmit a second subset of commands over the second bus, and transmit a third subset of commands over the third bus.

Abstract: Multiple wafers that each has multiple high-precision circuits and corresponding trim control circuits are batch trimmed in a process where each wafer is formed to include openings that expose trimmable circuit elements that are internal to the circuitry of the high-precision circuits. The high-precision circuits and trim control circuits are electrically activated during the trimming phase by metal traces that run along the saw streets. The method attaches a wafer contact structure to each wafer to electrically activate the metal traces. The method places the wafers with the wafer contact structures into a solution where the exposed trimmable circuit elements are electroplated or anodized when the actual output voltage of a high-precision circuit does not match the predicted output voltage of the high-precision circuit.

Abstract: A system and method is disclosed for providing an improved shutter for use with a shadow tab mask and heater table during a conditioning process for a physical vapor deposition (PVD) chamber. A shutter for covering the heater table is provided that has a circumferential flange with a thickness that is less than a thickness of the non-circumferential flange portions of the shutter. A shadow tab mask having a portion that extends over the flange portion is placed on the heater table. When deposition material is subsequently deposited, the reduced thickness of the flange portion prevents a fused seal from being formed between deposition material deposited on the shadow tab mask and deposition material deposited on the circumferential flange of the shutter.

Abstract: An interdigitated semiconductor capacitor with a large number of plates and a capacitance in the micro-farad range is formed on a wafer with only a single lithography step by depositing each odd layer of metal through a first shadow mask that lies spaced apart from the wafer, and each even layer of metal through a second shadow mask that lies spaced apart from the wafer.

Abstract: Arrangements for plating a single surface of a thin foil are described. In one aspect, a metal foil is wrapped tightly at least partially around a plating solution drum. The drum is partially immersed in a plating solution such that the waterline of the metal plating solution is below a break point where the metallic foil strip begins to unwind from the plating solution drum. With this arrangement, one side of the metallic foil strip is exposed to the metal plating solution, while the opposing back side of the metallic foil strip does not come in substantial contact with the metal plating solution. In this manner, the exposed side of the foil is plated while the back surface of the foil is not plated. The drum may be rotated to convey the foil through the plating solution.

Abstract: A group of high-performance like-polarity insulated-gate field-effect transistors (100, 108, 112, 116, 120, and 124 or 102, 110, 114, 118, 122, and 126) have selectably different configurations of lateral source/drain extensions, halo pockets, and gate dielectric thicknesses suitable for a semiconductor fabrication platform that provides a wide variety of transistors for analog and/or digital applications. Each transistor has a pair of source/drain zones, a gate dielectric layer, and a gate electrode. Each source/drain zone includes a main portion and a more lightly doped lateral extension. The lateral extension of one of the source/drain zones of one of the transistors is more heavily doped or/and extends less deeply below the upper semiconductor surface than the lateral extension of one of the source/drain zones of another of the transistors.

Abstract: A SiGe heterojunction bipolar transistor is fabricated by etching an epitaxially-formed structure to form a mesa that has a collector region, a cap region, and a notched SiGe base region that lies in between. A protective plug is formed in the notch of the SiGe base region so that thick non-conductive regions can be formed on the sides of the collector region and the cap region. Once the non-conductive regions have been formed, the protective plug is removed. An extrinsic base is then formed to lie in the notch and touch the base region, followed by the formation of isolation regions and an emitter region.

Abstract: A galvanic die has signal structures and a transformer structure that provide galvanically-isolated signal and power paths for a high-voltage die and a low-voltage die, which are both physically supported by the galvanic die and electrically connected to the signal and transformer structures of the galvanic die.

Abstract: A micro-electromechanical systems (MEMS) relay includes a switch with a first contact region and a second contact region that are vertically separated from each other by a gap. The MEMS relay requires a small vertical movement to close the gap and therefore is mechanically robust. In addition, the MEMS relay has a small footprint and, therefore, can be formed on top of small integrated circuits.

Abstract: A phase detection system for providing a phase signal indicative of a phase difference between first and second input signals, with the system including a pair of amplification channels for receiving the input signals, with each channel including a plurality of amplifier stages. The outputs of the two amplification channels are connected to the inputs of a multiplier arrangement, with the arrangement producing an uncompensated phase signal. Compensation circuitry is provided to receive a magnitude signal indicative of the relative magnitudes of the two input signals, with the magnitude signal being used to produce a corrected phase signal indicative of the phase difference between the two input signals.

Abstract: Control circuitry and method of controlling for a sampling phase lock loop (PLL). By controlling the duty cycle of a sampling control signal, in accordance with the PLL reference and output signals, spurious output signals from the sampling PLL being controlled can be reduced.

Abstract: A method includes receiving a variable reference voltage at a power converter and generating a regulated output voltage based on the variable reference voltage. The method also includes sequentially driving multiple sets of light emitting diodes (LEDs) using the regulated output voltage, where each set includes at least one LED. The variable reference voltage varies based on the set of LEDs being driven. For example, the method could include receiving a first reference voltage, generating a first output voltage based on the first reference voltage, and driving a first set of LEDs using the first output voltage. The method could then include receiving a second reference voltage, generating a second output voltage based on the second reference voltage, and driving a second set of LEDs using the second output voltage. At least one additional set of LEDs could be driven concurrently with the sequential driving of the multiple sets of LEDs.

Abstract: A master modem is configured to generate a carrier signal for transmission over a wired connection. A slave modem is configured to change an impedance of the wired connection to alter generation of the carrier signal by the master modem. The impedance of the wired connection is changed based on data to be provided by the slave modem. The master modem can demodulate its own carrier signal to obtain the data provided by the slave modem. The impedance of the wired connection could be changed by changing an impedance of a transformer winding or inductor of the slave modem, where the transformer winding or inductor is coupled to the wired connection. The impedance of the wired connection could also be changed by changing a reactance of a circuit coupled to the wired connection.

Abstract: A system and method for processing close talking differential microphone array (CTDMA) signals in which incoming microphone signals are transformed from time domain signals to frequency domain signals having separable magnitude and phase information. Processing of the frequency domain signals is performed using the magnitude information, following which phase information is reintroduced using phase information of one of the original frequency domain signals. As a result, high pass filtering effects of conventional differential signal processing of CTDMA signals are substantially avoided.

Abstract: A non-volatile memory cell includes NMOS programming, read, erase, and control transistors having gate electrodes connected to a storage node. The erase and control transistors have interconnected source, drain, and bulk electrodes. The cell is programmed by setting source, drain, bulk, and gate electrodes of all transistors to a positive voltage. An inhibiting voltage is applied to source, drain, and bulk electrodes of the read transistor, while setting source and drain electrodes of the programming transistor to the positive voltage and the bulk electrode of the programming transistor to the positive voltage or the inhibiting voltage. Source, drain, and bulk electrodes of the control transistor are then ramped to a negative control voltage while ramping source, drain, and bulk electrodes of the erase transistor to a negative erase voltage and then back to the positive voltage. Source, drain.

Abstract: Low voltage differential signaling (LVDS) circuitry and method for dynamically controlling the common mode voltage at the input of an LVDS receiver. The common mode voltage of the incoming LVDS signal is monitored. The common mode voltage at the input of the LVDS receiver is clamped at a clamp voltage when the common mode voltage of the incoming LVDS signal is less than a predetermined voltage, and allowed to track it otherwise.