Abstract: Circuitry for adaptive signal equalizing with coarse and fine boost controls by providing multiple serially coupled stages of parallel controllable DC and AC signal gains with coarse and fine gain controls provided across all stages.

Abstract: A method includes generating an electrical signal representing a magnetic field using a magnetic field sensor having alternating layers of magneto-strictive material and piezo-electric material. The method also includes performing up-conversion or down-conversion so that the electrical signal representing the magnetic field has a higher or lower frequency than a frequency of the magnetic field. The up-conversion or down-conversion is performed before the magnetic field is converted into the electrical signal. The up-conversion or down-conversion could be performed by repeatedly sensitizing and desensitizing the magnetic field sensor. This could be done using a permanent magnet and an electromagnet, an electromagnet without a permanent magnet, or a movable permanent magnet. The up-conversion or down-conversion could also be performed by chopping the magnetic field.

Abstract: An apparatus includes a delay line having at least two parallel branches, where each branch includes multiple delay cells coupled in series. The delay line is configured to receive an input signal and to propagate the input signal in parallel through the delay cells in the branches. The apparatus also includes multiple sampling circuits configured to sample the input signal at different taps in the branches of the delay line and to output sampled values. The taps in a first of the branches are associated with different amounts of delay compared to the taps in a second of the branches. At least some of the delay cells in the branches of the delay line could have a minimum delay, and a difference in delay between at least one tap in the first branch and at least one tap in the second branch could be less than a smallest of the minimum delays.

Abstract: In one aspect, the present invention relates generally to integrated circuit (IC) packages and more specific to some embodiments of IC power convertor technologies. In particular, IC packages that have a high degree of scalability to handle high voltage or current levels, good heat dissipation properties, flexible adaptability to generate packages operable at a wide range of current levels and having a wide range of power adaptability, lends itself to rapid inexpensive prototyping, the ability to adapt various substrates and IC devices to one another without extensive retooling or custom designing of components, as well as other advantages.

Abstract: In an extended drain MOS device used in high voltage applications, switching characteristics are improved by providing for at least one base contact in the active region in the extended drain space.

Abstract: In an SCR ESD protection circuit, the n-type emitter of the SCR is controlled to receive electron current only during an ESD event, thereby defining PNP characteristics during normal operation and SCR characteristics during an ESD event.

Abstract: An apparatus includes terminals configured to be coupled to a string wiring of a photovoltaic string. The apparatus also includes a power controller configured to control a power provided over the string wiring by a photovoltaic panel in the photovoltaic string. The apparatus further includes a wireless radio configured to at least one of transmit and receive wireless signals using the string wiring as an antenna. The wireless signals contain data associated with the photovoltaic panel and/or the power controller. For example, the wireless radio could be configured to receive a first signal containing a command for the power controller from the string wiring and to provide the command to the power controller. The wireless radio could also be configured to receive an acknowledgement associated with the command from the power controller and to transmit a second signal containing the acknowledgement over the string wiring for wireless transmission.

Abstract: A system includes a touch screen having multiple electrodes. The system also includes a processing unit configured to use the electrodes to (i) detect an object contacting the touch screen or within a first distance from the touch screen in a first mode and (ii) detect the object within a second distance from the touch screen in a second mode. The second distance is larger than the first distance. The processing unit can be configured to use the multiple electrodes in the first mode to perform capacitive touch screen sensing. The processing unit can also be configured to use the multiple electrodes in the second mode to perform electric field sensing.

Abstract: An electrically programmable read only memory (EPROM) BIT cell structure formed on a semiconductor substrate comprises an N-type epitaxial layer formed on the semiconductor substrate, an N-type well region formed in the epitaxial layer, LOCOS field oxide formed at the periphery of the well region to define an active device region in the well region, a field oxide ring formed in the active region and space-apart from the LOCOS field oxide to define an EPROM BIT cell region, and an EPROM BIT cell formed in the EPROM BIT cell region.

Abstract: In the case of adjacent high voltage nodes in which one node is protected by a lateral BJT clamp, the irreversible burnout due to transient latch-up between the two adjacent high voltage pins of the structure is avoided by increasing the base contact region by including a sinker connected to the base.

Abstract: A method includes receiving a sense signal having multiple pulses, where the sense signal is based on an output of a dimmer. The method also includes, for each of multiple sampling periods, sampling a subset of the pulses in the sense signal during that sampling period. The method further includes generating a holding current for the dimmer during the sampling of the subset of pulses in at least one of the sampling periods. In addition, the method includes, for each of the sampling periods, generating an output value identifying a duty cycle for driving one or more light emitting diodes (LEDs). The subset of pulses in each of the sampling periods includes multiple pulses during that sampling period but not one or more initial pulses at a beginning of that sampling period.

Abstract: An apparatus and method for wafer level fabrication of high value inductors directly on top of semiconductor integrated circuits. The apparatus and method includes fabricating a semiconductor wafer including a plurality of dice, each of the dice including power circuitry and a switching node. Once the wafer is fabricated, then a plurality of inductors are fabricated directly onto the plurality of dice on the wafer respectively. Each inductor is fabricated by forming a plurality of magnetic core inductor members on an interconnect dielectric layer formed on the wafer. An insulating layer, and then inductor coils, are then formed over the plurality of magnetic core inductor members over each die. A plated magnetic layer is formed over the plurality of inductors respectively to raise the permeability and inductance of the structure.

Abstract: A lateral DMOS transistor formed on a silicon-on-insulator (SOI) structure has a higher breakdown voltage that results from a cavity that is formed in the bulk region of the SOI structure. The cavity exposes a portion of the bottom surface of the insulator layer of the SOI structure that lies directly vertically below the drift region of the DMOS transistor.

Abstract: In an LVTSCR, an avalanche diode based control circuit controls both the base of the internal PNP of the LVTSCR as well as the gate of the LVTSCR.

Abstract: A galvanic isolation integrated circuit system includes a semiconductor substrate; a layer of thermally conductive material, e.g., CVD nano- or poly-diamond thin film or boron nitride CVD thin film, formed over the semiconductor substrate; a first integrated circuit structure formed over the layer of thermally conductive material; a second integrated circuit structure formed over the layer of thermally conductive material, the second integrated circuit structure being spaced apart from the first integrated circuit structure; and a galvanic isolation structure formed over the layer of thermally conductive material between the first and second integrated circuit structures and connected to the first integrated circuit structure and the second integrated circuit structure.

Abstract: Methods and systems are described for enabling the efficient fabrication of small form factor power converters and also the small form factor power converter devices.

Abstract: The Si substrate of a group III-N HEMT is formed in layers that define a p-n junction which electrically isolates an upper region of the Si substrate from a lower region of the Si substrate. As a result, the upper region of the Si substrate can electrically float, thereby obtaining a full buffer breakdown voltage, while the lower region of the Si substrate can be attached to a package by way of a conductive epoxy, thereby significantly improving the thermal conductivity of the group III-N HEMT and minimizing undesirable floating-voltage regions.

Abstract: Decision feedback equalization (DFE) circuitry and method for equalizing data signals over a wide range of data rates. By using delayed and controlled versions of the recovered data clock to retime the equalized data signal for feedback via the DFE taps, correct feedback signal timing is maintained and jitter tolerance is increased at high data rates.

Abstract: A method includes forming at least one control gate over a semiconductor substrate. The method also includes depositing a layer of conductive material over the at least one control gate and the semiconductor substrate. The method further includes etching the layer of conductive material to form multiple spacers adjacent to the at least one control gate, where at least one of the spacers forms a floating gate in at least one memory cell. Two spacers could be formed adjacent to the at least one control gate, and one of the spacers could be etched so that a single memory cell includes the control gate and the remaining spacer. Also, two spacers could be formed adjacent to the at least one control gate, and the at least one control gate could be etched and separated to form multiple control gates associated with different memory cells.

Abstract: A system and method is disclosed for minimizing power consumption of a sensor unit that is capable of detecting an object. Main circuitry operates the sensor unit in a high power mode of operation when the sensor unit detects an object. Low power control circuitry operates the sensor unit in a low power mode of operation when the sensor unit does not detect an object within a pre-determined period of time. The low power control circuitry also comprises a counter to periodically determine when to restore the sensor unit to a high power mode of operation. One advantageous embodiment of the sensor unit is a fingerprint sensor unit for detecting a finger to obtain fingerprint information.