Abstract: A method for evaluating a biological effect of far infrared (FIR) includes the following. An FIR radiation source is provided to emit FIR. An FIR biological effect index (FBI) of the FIR is measured. A ratio of a blood glucose level change of an experimental group irradiated with the FIR to a blood glucose level change of a control group not irradiated with FIR is defined as the FBI. When the FBI is greater than 1, it is evaluated that the FIR causes a biological effect on an organism.

Abstract: A memory device includes a memory cell, a writing transistor, and a reading transistor. The memory cell includes a semiconductor substrate, a tunneling layer, a storage layer, a first electrode, a second electrode, and a third electrode. The tunneling layer is over the semiconductor substrate. The storage layer is on the tunneling layer. The first electrode is on the storage layer. The second electrode is on the tunneling layer. The storage layer has a sidewall facing the second electrode. The third electrode is spaced apart from the second electrode. The writing transistor is electrically connected to the first electrode of the memory cell. The reading transistor is electrically connected to the second electrode of the memory cell.

Abstract: The present disclosure provides a method for detecting short-chain fatty acids in biological samples, including a derivatizing step, a loading step and a detecting step. The derivatizing step includes treating the short-chain fatty acids in the biological sample with 2-nitrophenylhydrazine for derivatizing the short-chain fatty acids into a sample to be detected. The loading step includes loading the sample onto a paper carrier. The detecting step includes analyzing the sample loaded onto the paper carrier by direct analysis in real time mass spectrometry for obtaining a detection result. The method provided by the present disclosure may complete the analysis of the biological sample within a short period of time and achieve a quantitative result comparable to that obtained by conventional chromatographic approaches.

Abstract: A memory device includes a spin-orbit-transfer (SOT) bottom electrode, an SOT ferromagnetic free layer, a first tunnel barrier layer, a spin-transfer-torque (STT) ferromagnetic free layer, a second tunnel barrier layer and a reference layer. The SOT ferromagnetic free layer is over the SOT bottom electrode. The SOT ferromagnetic free layer has a magnetic orientation switchable by the SOT bottom electrode using a spin Hall effect or Rashba effect. The first tunnel barrier layer is over the SOT ferromagnetic free layer. The STT ferromagnetic free layer is over the first tunnel barrier layer and has a magnetic orientation switchable using an STT effect. The second tunnel barrier layer is over the STT ferromagnetic free layer. The second tunnel barrier layer has a thickness different from a thickness of the first tunnel barrier layer. The reference layer is over the second tunnel barrier layer and has a fixed magnetic orientation.

Abstract: Provided is a method of using an aptamer for detecting a glycated hemoglobin in a whole blood, the method includes that the aptamer is provided, the aptamer includes a DNA sequence selected from the group consisting of derived sequences of SEQ ID NOs: 1, 2, 3, and 4, in which the derived sequences refer to that 3? end and/or 5? end of the derived sequences are modified, and the derived sequences have 90% identity to the SEQ ID NOs: 1, 2, 3, and 4. The aptamer and the whole blood are contacted. A concentration of a conjugate of the aptamer and the glycated hemoglobin is estimated. Provided also is a nanoelectronic aptasensor including the above aptamer.

Abstract: An IC structure comprises an MTJ cell, a transistor, a first word line, and a second word line. The transistor is electrically coupled to the MTJ cell. The transistor comprises a first gate terminal and a second gate terminal independent of the first gate terminal. The first word line is electrically coupled to the first gate terminal of the transistor. The second word line is electrically coupled to the second gate terminal of the transistor. A resistance state of the MTJ cell is dependent on a first word line voltage applied to the first word line and a second word line voltage applied to the second word line, and the resistance state of the MTJ cell follows an AND gate logic or an OR gate logic.

Abstract: A semiconductor memory device includes a transistor having a gate, a source and a drain and a metal-insulator-semiconductor (MIS) structure. The transistor and the MIS structure are disposed on a common substrate. The MIS structure includes a dielectric layer disposed on a semiconductor region, and an electrode electrically disposed on the dielectric layer and coupled to the drain of the transistor. The electrode includes a bulk portion and a high-resistance portion, both disposed on the dielectric layer. The high-resistance portion has a resistance value in a range from 1.0×10?4 ?cm to 1.0×104 ?cm or a sheet resistance in a range from 1.0×102?/? to 1.0×1010?/?.

Abstract: A device is provided. The device includes a physical unclonable function (PUF) cell array. The PUF cell array includes multiple bit cells, and generates a PUF response output, in response to a challenge input, based on a data state of one bit cell in the bit cells. Each of the bit cells stores a bit data and includes a transistor having a control terminal coupled to a word line and a first terminal coupled to a source line, a first memory cell having a first terminal coupled to a first data line and a second terminal coupled to a second terminal of the transistor, and a second memory cell having a first terminal coupled to a second data line, different from the first data line, and a second terminal coupled to the second terminal of the first memory cell at the second terminal of the transistor.

Abstract: An integrated circuit includes a substrate, a transistor over the substrate, a first inter-metal dielectric (IMD) layer over the transistor, a metal via in the first IMD layer, a first 2-D material layer cupping an underside of the metal via, a second IMD layer over the metal via, a metal line in the second IMD layer, and a second 2-D material layer cupping an underside of the metal line. The second 2-D material layer span across the metal via and the first 2-D material layer.

Abstract: A flash memory device includes a substrate, a semiconductor quantum well layer, a semiconductor spacer, a semiconductor channel layer, a gate structure, and source/drain regions. The semiconductor quantum well layer is formed of a first semiconductor material and is disposed over the substrate. The semiconductor spacer is formed of a second semiconductor material and is disposed over the first semiconductor channel layer. The semiconductor channel layer is formed of the first semiconductor material and is disposed over the semiconductor spacer. Thea gate structure is over the second semiconductor channel layer. The source/drain regions are over the substrate and are on opposite sides of the gate structure.

Abstract: The present invention discloses a partially crosslinked hydrogels blended composition with enhanced viscosity and yield stress, which is formed by the polymerization of one or more colloid monomers through crosslinking. The polymerization is initiated by a photoinitiator under irradiation of the light of a specific wavelength, which promotes crosslinking of the one or more colloid monomers. The hydrogels blended composition can be further crosslinked with one or more other colloid monomers through repeated excitation of the photoinitiator. The hydrogels blended composition can be polymerized into a gel upon re-irradiation, and can also be used as a biomaterial for wound repair, three-dimensional cell culture, personal nursing care, health care, medical and pharmaceutical applications.

Abstract: A method includes forming a semiconductive channel layer on a substrate. A dummy gate is formed on the semiconductive channel layer. Gate spacers are formed on opposite sides of the dummy gate. The dummy gate is removed to form a gate trench between the gate spacers, resulting in the semiconductive channel layer exposed in the gate trench. A semiconductive protection layer is deposited in the gate trench and on the exposed semiconductive channel layer. A top portion of the semiconductive protection layer is oxidized to form an oxidation layer over a remaining portion of the semiconductive protection layer. The oxidation layer is annealed after the top portion of the semiconductive protection layer is oxidized. A gate structure is formed over the semiconductive protection layer and in the gate trench after the oxidation layer is annealed.

Abstract: A method for forming an integrated circuit device is provided. The method includes forming a transistor over a frontside of a substrate; forming an interconnect structure over the transistor; depositing a first transition metal layer over the interconnect structure; performing a plasma treatment to turn the first transition metal layer into a first transition metal dichalcogenide layer; forming a dielectric layer over the first transition metal dichalcogenide layer; forming a first gate electrode over the dielectric layer and a first portion of the first transition metal dichalcogenide layer; and forming a first source contact and a first drain contact respectively connected with a second portion and a third portion of the first transition metal dichalcogenide layer, the first portion of the first transition metal dichalcogenide layer being between the second and third portions of the first transition metal dichalcogenide layers.

Abstract: A device includes plural semiconductor fins, a gate structure, an interlayer dielectric (ILD) layer, and an isolation dielectric. The gate structure is across the semiconductor fins. The ILD surrounds the gate structure. The isolation dielectric is at least between the semiconductor fins and has a thermal conductivity greater than a thermal conductivity of the ILD layer.

Abstract: An antenna measurement system includes an array of antennas, an array of reflectors, and a measurement surface. The array of antennas includes a plurality of antenna elements arranged in a straight line; any two adjacent antenna elements in the above antenna elements are separated by a predetermined distance, and each of the antenna elements in the above antenna elements has a radiator and a feed point. The array of reflectors includes at least one reflector and is arranged in a width direction or a height direction, and the array of reflectors is configured to generate a reflection signal according to a signal sent by the array of antennas. An antenna to be measured is configured to perform a measurement operation on the reflection signal on the measurement surface.

Abstract: An interleaved three-phase Y-Delta connected power converter is provided. The interleaved three-phase Y-Delta connected power converter includes an input voltage source, an input capacitor, a first converter module, a second converter module, an output circuit, and a control circuit. The control circuit calculates a phase shift amount and an operating frequency through voltage and current feedbacks to generate a plurality of switch signal groups for controlling the first converter module and the second converter module, respectively.

Abstract: The subject disclosure provides a simple, fast, and high-yield method for encapsulating solar cells. This method can produce an encapsulation of solar cell(s) that is flat, bubble-free, lightweight, and flexible. In addition, it can also reduce equipment and material costs.

Abstract: A method and a system for generating a multiview stereoscopic image are provided. The method includes the following steps. An image capturing apparatus captures a real calibration panel to obtain multiple images, and a processor obtains a datum image and multiple images to be calibrated by analyzing the images including the real calibration panel. The processor respectively calculates a homography matrix of each of the images to be calibrated corresponding to the datum image according to the datum image and the images to be calibrated. The processor obtains a calibration matrix of the homography matrix by performing a matrix disassembly calculation on each of the homography matrices. The processor multiplies the images to be calibrated by the corresponding calibration matrix to obtain multiple calibrated images. The processor outputs the multiview stereoscopic image including the datum image and the calibrated images.

Abstract: A robotic arm comprising an operation end, a base, a sensor unit and a control unit is provided. The operation end is connected to the base, and the operation end is configured to reach an operational area. The sensor unit provides a sensor signal according to the force applied by or the motion of an operator. When the operation end reaches the operational area, the control unit sets a fixed position on the robotic arm between the base and the operation end. When the sensor signal from the operator fulfills a default condition, the control unit moves the robotic arm away from the operator, without moving the fixed position on the robotic arm.

Abstract: A semiconductor device includes a semiconductor fin protruding from a substrate, a gate electrode over the semiconductor fin, a gate insulating layer between the semiconductor fin and the gate electrode, source and drain regions disposed on opposite sides of the semiconductor fin, a first stressor formed in a region between the source and drain regions. The first stressor including one material selected from the group consisting of He, Ne, and Ga.