Patents Assigned to National University Corporation Tohoku University
  • Patent number: 8138527
    Abstract: An accumulation mode transistor has an impurity concentration of a semiconductor layer in a channel region at a value higher than 2×1017 cm?3 to achieve a large gate voltage swing.
    Type: Grant
    Filed: July 12, 2007
    Date of Patent: March 20, 2012
    Assignees: National University Corporation Tohoku University, Foundation For Advancement of International Science
    Inventors: Tadahiro Ohmi, Akinobu Teramoto, Rihito Kuroda
  • Publication number: 20120048502
    Abstract: In a method for producing a salt core for casting formed by a molten salt made of a salt mixture containing sodium salt, first, a melt is formed by heating a salt mixture. Next, a mold for core molding is heated to a temperature higher than about 0.52×Tm and lower than about 0.7×Tm. Note that Tm represents the liquidus temperature of the salt mixture as an absolute temperature (K). Then, the melt is poured under pressure into the mold heated as described above. A salt core for casting is molded by solidifying the melt inside the mold.
    Type: Application
    Filed: April 30, 2010
    Publication date: March 1, 2012
    Applicants: YAMAHA HATSUDOKI KABUSHIKI KAISHA, NATIONAL UNIVERSITY CORPORATION TOHOKU UNIVERSITY
    Inventors: Koichi Anzai, Katsunari Oikawa, Youji Yamada
  • Patent number: 8120016
    Abstract: A solid-state imaging device, a line sensor and an optical sensor for enhancing a wide dynamic range while keeping high sensitivity with a high S/N ratio, and a method of operating a solid-state imaging device for enhancing a wide dynamic range while keeping high sensitivity with a high S/N ratio are provided. The solid-state imaging device comprises an integrated array of a plurality of pixels, each of which comprises a photodiode PD for receiving light and generating photoelectric charges, a transfer transistor Tr1 for transferring the photoelectric charges, and a storage capacitor element C connected to the photodiode PD at least through the transfer transistor Tr1 for accumulating, at least through the transfer transistor Tr1, the photoelectric charge overflowing from the photodiode PD during accumulating operation.
    Type: Grant
    Filed: December 4, 2008
    Date of Patent: February 21, 2012
    Assignee: National University Corporation Tohoku University
    Inventor: Shigetoshi Sugawa
  • Publication number: 20120008142
    Abstract: A method of attaching an object to be measured to a structure causing a diffraction phenomenon; irradiating the structure to which the object to be measured is attached and which causes the diffraction phenomenon with an electromagnetic wave; detecting the electromagnetic wave scattered by the structure causing the diffraction phenomenon; and measuring a characteristic of the object to be measured from the frequency characteristic of the detected electromagnetic wave. The object to be measured is attached directly to the surface of the structure causing the diffraction phenomenon. Thus, the method for measuring the characteristic of an object to be measured exhibits an improved measurement sensitivity and high reproducibility. A structure causing a diffraction phenomenon and used for the method, and a measuring device are provided.
    Type: Application
    Filed: September 22, 2011
    Publication date: January 12, 2012
    Applicants: National University Corporation Tohoku University, MURATA MANUFACTURING CO., LTD.
    Inventors: Seiji Kamba, Takashi Kondo, Koji Tanaka, Kazuhiro Takigawa, Yuichi Ogawa
  • Patent number: 8093918
    Abstract: An electronic device that includes an actual operation circuit that operates during an actual operation of the electronic device, a second test circuit and a third test circuit that operate during a test of the electronic device, and a power supply section. The power supply section, during the actual operation of the electronic device, does not apply a power supply voltage to the second test circuit and applies power supply voltages to the actual operation circuit and the third test circuit. The power supply section, to obtain identification of the electronic device, applies a power supply voltage to the second test circuit.
    Type: Grant
    Filed: August 18, 2010
    Date of Patent: January 10, 2012
    Assignees: National University Corporation Tohoku University, Advantest Corporation
    Inventors: Toshiyuki Okayasu, Shigetoshi Sugawa, Akinobu Teramoto
  • Publication number: 20110307014
    Abstract: A spinal fixation titanium alloy rod fixes a plurality of spinal-fixing screws embedded and fixed in vertebrae of a human body. The rod is cylindrically shaped, has a sufficient length for coupling with the spinal-fixing screws, and has a diameter adjusted to 4 to 7 mm. In the titanium alloy constituting the rod, Nb content is 25 to 35 percent by weight, Ta content is such that the Nb content+0.8×Ta content ranges from 36 to 45 percent by weight, Zr content is 3 to 6 percent by weight, and the remainder is Ti and unavoidable impurities, excluding vanadium. The titanium alloy is manufactured by swaging processing at a cross-sectional reduction rate of at least 90%, and aging the swaged titanium alloy by heating at a temperature of 600 to 800K, preferably 700 to 800K, for 43.2 ks to 604.8 ks.
    Type: Application
    Filed: December 10, 2010
    Publication date: December 15, 2011
    Applicants: NATIONAL UNIVERSITY CORPORATION TOHOKU UNIVERSITY, SHOWA-IKA KOGYO CO. LTD.
    Inventors: Mitsuo Niinomi, Masaaki Nakai, Kengo Narita
  • Publication number: 20110253945
    Abstract: The invention is directed to a carbon material dispersion, including: a fluorinated carbon material having a fluorinated surface formed by bringing a treatment gas with a fluorine concentration of 0.01 to 100 vol % into contact with a carbon material under conditions at 150 to 600° C.; and a dispersion medium in which the fluorinated carbon material is dispersed.
    Type: Application
    Filed: December 18, 2009
    Publication date: October 20, 2011
    Applicants: STELLA CHEMIFA CORPORATION, NATIONAL UNIVERSITY CORPORATION TOHOKU UNIVERSITY
    Inventors: Kazuyuki Tohji, Yoshinori Sato, Shinji Hashiguchi, Kazutaka Hirano
  • Publication number: 20110248323
    Abstract: In the plasma-based ion implantation for accelerating positive ions of a plasma and implanting the positive ions into a substrate to be processed on a holding stage in a processing chamber where the plasma has been excited, ion implantation is achieved in the following manner: an RF power having a frequency of 4 MHz or greater is applied to the holding stage to cause a self-bias voltage to generate on the surface of the substrate. The RF power is applied a plurality of times in the form of pulses.
    Type: Application
    Filed: December 10, 2009
    Publication date: October 13, 2011
    Applicant: NATIONAL UNIVERSITY CORPORATION TOHOKU UNIVERSITY
    Inventors: Tadahiro Ohmi, Tetsuya Goto
  • Publication number: 20110215384
    Abstract: In manufacturing processes of a semiconductor device including a shallow trench element isolation region and an interlayer insulating film of a multilayer structure, it is necessary to repeatedly use CMP, but since the CMP itself is costly, the repeated use of the CMP is a cause to increase the manufacturing cost. As an insulating film for use in a shallow trench (ST) element isolation region and/or a lowermost-layer interlayer insulating film, use is made of an insulating coating film that can be coated by spin coating. The insulating coating film has a composition expressed by ((CH3)nSiO2-n/2)x(SiO2)1-x(where n=1 to 3 and 0?x?1.0) and a film with a different relative permittivity k is formed by selecting heat treatment conditions. The STI element isolation region can be formed by modifying the insulating coating film completely to a SiO2 film, while the interlayer insulating film with a small relative permittivity k can be formed by converting it to a state not completely modified.
    Type: Application
    Filed: August 14, 2008
    Publication date: September 8, 2011
    Applicants: National University Corporation Tohoku University, Tokyo Electron Limited, Ube Industries, Ltd., Ube-Nitto Kasei Co., Ltd.
    Inventors: Tadahiro Ohmi, Takaaki Matsuoka, Atsutoshi Inokuchi, Kohei Watanuki, Tadashi Koike, Tatsuhiko Adachi
  • Publication number: 20110212552
    Abstract: There is provided a wafer on which a plurality of electronic devices and circuits under test are to be formed, where each circuit under test includes a plurality of transistors under measurement provided in electrically parallel, a selecting section which sequentially selects the respective transistors under measurement, and an output section which sequentially outputs the source voltages of the transistors under measurement sequentially selected by the selecting section.
    Type: Application
    Filed: May 5, 2011
    Publication date: September 1, 2011
    Applicant: NATIONAL UNIVERSITY CORPORATION TOHOKU UNIVERSITY
    Inventors: SHIGETOSHI SUGAWA, AKINOBU TERAMOTO
  • Publication number: 20110209567
    Abstract: There is provided a wafer on which a plurality of electronic devices and circuits under test are to be formed, where each circuit under test includes a plurality of transistors under measurement provided in electrically parallel, a selecting section which sequentially selects the respective transistors under measurement, and an output section which sequentially outputs the source voltages of the transistors under measurement sequentially selected by the selecting section.
    Type: Application
    Filed: May 5, 2011
    Publication date: September 1, 2011
    Applicant: NATIONAL UNIVERSITY CORPORATION TOHOKU UNIVERSITY
    Inventors: SHIGETOSHI SUGAWA, AKINOBU TERAMOTO
  • Patent number: 7994063
    Abstract: Disclosed is a method for cleaning a semiconductor substrate that can solve a problem of a conventional cleaning method which should include at least five steps for cleaning a substrate such as a semiconductor substrate. The method for cleaning a semiconductor substrate comprises a first step of cleaning a substrate with ultrapure water containing ozone, a second step of cleaning the substrate with ultrapure water containing a surfactant, and a third step of removing an organic compound derived from the surfactant, with a cleaning liquid containing ultrapure water and 2-propanol. After the third step, plasma of noble gas such as krypton is applied to the substrate to further remove the organic compound derived from the surfactant.
    Type: Grant
    Filed: April 10, 2009
    Date of Patent: August 9, 2011
    Assignees: National University Corporation Tohoku University, Stella Chemifa Corporation
    Inventors: Tadahiro Ohmi, Akinobu Teramoto, Rui Hasebe, Masayuki Miyashita
  • Publication number: 20110177355
    Abstract: Provided is an Al alloy member with an excellent mechanical strength that is sufficient for use in large-scale manufacturing apparatuses. The Al alloy member is characterized in that, in mass %, Mg concentration is 5.0% or less, Ce concentration is 15% or less, Zr concentration is 0.15% or less, the balance comprises Al and unavoidable impurities, the elements of the unavoidable impurities are respectively 0.01% or less, and the Vickers hardness of the Al alloy member is greater than 30.
    Type: Application
    Filed: July 28, 2009
    Publication date: July 21, 2011
    Applicants: National University Corporation Tohoku University, Nippon Light Metal Company, Ltd.
    Inventors: Tadahiro Ohmi, Masafumi Kitano, Minoru Tahara, Hisakazu Ito, Kota Shirai, Masayuki Saeki
  • Patent number: 7977796
    Abstract: A gas or an insulating material having a relative dielectric constant of not more than 2.5 on average is interposed between a first wiring layer and a second wiring layer included in a multilayer wiring structure. Between a wiring of the first wiring layer and a wiring of the second wiring layer, a conductive connector is arranged. Between a predetermined wiring of the first wiring layer and a predetermined wiring of the second wiring layer, an insulating heat conductor having a relative dielectric constant of not more than 5 is arranged.
    Type: Grant
    Filed: August 24, 2007
    Date of Patent: July 12, 2011
    Assignees: National University Corporation Tohoku University, Foundation for Advancement of International Science
    Inventor: Tadahiro Ohmi
  • Patent number: 7965097
    Abstract: There is provided a wafer on which a plurality of electronic devices and circuits under test are to be formed, where each circuit under test includes a plurality of transistors under measurement provided in electrically parallel, a selecting section which sequentially selects the respective transistors under measurement, and an output section which sequentially outputs the source voltages of the transistors under measurement sequentially selected by the selecting section.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: June 21, 2011
    Assignee: National University Corporation Tohoku University
    Inventors: Shigetoshi Sugawa, Akinobu Teramoto
  • Publication number: 20110127075
    Abstract: An insulative coat film comprising one or two or more kinds of oxides having a dielectric constant (k) of 2.5 or smaller and expressed by a general formula of ((CH3)nSiO2-n/2)x(SiO2)1-x (where n=1 to 3, x?1) is used to form an interlayer insulation film. The insulative coat film applied by spin-coating is flat without reflecting underlying unevenness, and the heat-treated film has surface roughness of 1 nm or less in Ra and 20 nm or less in a P-V value. The interlayer insulation film containing the insulative coat film can have a wiring structure and an electrode formed only by etching without need of a CMP process.
    Type: Application
    Filed: August 14, 2008
    Publication date: June 2, 2011
    Applicants: NATIONAL UNIVERSITY CORPORATION TOHOKU UNIVERSITY, TOKYO ELECTRON LIMITED, UBE INDUSTRIES, LTD., UBE-NITTO KASEI CO., LTD.
    Inventors: Tadahiro Ohmi, Takaaki Matsuoka, Atsutoshi Inokuchi, Kohei Watanuki, Tadashi Koike, Tatsuhiko Adachi
  • Publication number: 20110120566
    Abstract: A fluid flow rate control method is provided that uses a flow rate range variable type pressure type flow rate control device provided with at least two or more parallel fluid passages disposed between the downstream side of a control valve of the control device and a fluid supply pipe passage, and orifices having different fluid flow rate characteristics are respectively interposed in parallel fluid passages to pass fluid in a first flow rate region through one orifice for flow rate control, and to pass fluid in a second flow rate region through at least another orifice for flow rate control. Flow rate characteristics of the respective orifices are selected so that a maximum controllable flow rate of fluid in the first flow rate region at low flow rate is smaller than 10% of a maximum controllable flow rate in the second flow rate region at high flow rate.
    Type: Application
    Filed: November 19, 2010
    Publication date: May 26, 2011
    Applicants: FUJIKIN INCORPORATED, NATIONAL UNIVERSITY CORPORATION TOHOKU UNIVERSITY, TOKYO ELECTRON LIMITED
    Inventors: Tadahiro OHMI, Kouji NISHINO, Ryousuke DOHI, Masaaki NAGASE, Katsuyuki SUGITA, Kaoru HIRATA, Takashi HIROSE, Tsutomu SHINOHARA, Nobukazu IKEDA, Toshihide YOSHIDA, Hisashi TANAKA
  • Patent number: 7902595
    Abstract: In one embodiment of the present invention, a power IC device is disclosed containing a power MOS transistor with a low ON resistance and a surface channel MOS transistor with a high operation speed. There is also provided a method of manufacturing such a device. A chip has a surface of which the planar direction is not less than ?8° and not more than +8° off a silicon crystal face. The p-channel trench power MOS transistor includes a trench formed vertically from the surface of the chip, a gate region in the trench, an inversion channel region on a side wall of the trench, a source region in a surface layer of the chip, and a drain region in a back surface layer of the chip. The surface channel MOS transistor has an inversion channel region fabricated so that an inversion channel current flows in a direction not less than ?8° and not more than +8° off the silicon crystal direction.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: March 8, 2011
    Assignees: Sharp Kabushiki Kaisha, National University Corporation Tohoku University, Yazaki Corporation
    Inventors: Alberto O. Adan, Mitsuhiro Kikuta, Akinobu Teramoto, Tadahiro Ohmi, Hiroo Yabe, Takanori Watanabe
  • Publication number: 20110049718
    Abstract: When a barrier film is formed on an exposed surface of an interlayer insulation film on a substrate, the interlayer insulation film having a recess formed therein, and a metal wiring to be electrically connected to a metal wiring in a lower layer is formed in the recess, a barrier film having an excellent step coverage can be formed and increase of a wiring resistance can be restrained. An oxide film on a surface of the lower copper wiring exposed to a bottom surface of the interlayer insulation film is reduced or edged so as to remove oxygen on the surface of the copper wiring. Then, by supplying an organic metal compound containing manganese and containing no oxygen, generation of manganese oxide as a self-forming barrier film is selectively allowed on an area containing oxygen, such as a sidewall of the recess and a surface of the interlayer insulation film, while generation of the manganese oxide is not allowed on the surface of the copper wiring. Thereafter, copper is embedded in the recess.
    Type: Application
    Filed: January 20, 2009
    Publication date: March 3, 2011
    Applicants: TOKYO ELECTRON LIMITED, NATIONAL UNIVERSITY CORPORATION TOHOKU UNIVERSITY
    Inventors: Kenji Matsumoto, Hitoshi Itoh, Hiroshi Sato, Junichi Koike, Koji Neishi
  • Patent number: 7898733
    Abstract: A laser oscillator includes a ring resonator. The ring resonator includes an optical circulator having first, second, third, and fourth ports and a first optical amplification fiber connected to the optical circulator. Light incident on the first port is exited from the second port, and light incident on the second port is exited from the third port. The fourth port provides an exciting light and injects the exciting light into the ring resonator through the first port. The first optical amplification fiber amplifies light exited from the third port with the exciting light provided by the fourth port. The laser oscillator also includes an optical member connected to the optical circulator. The optical member reflects at least a part of the light exited from the second port and injects the same into the second port again.
    Type: Grant
    Filed: April 13, 2009
    Date of Patent: March 1, 2011
    Assignees: Advantest Corporation, National University Corporation Tohoku University
    Inventors: Kazunori Shiota, Shin Masuda, Masataka Nakazawa, Masato Yoshida