Patents Assigned to National University Corporation Tohoku University
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Publication number: 20110041768Abstract: A heat equalizer includes a container structure having a heating block in which a working fluid is held for heating and vaporizing a material to be heated, a heater placed at the bottom of the container structure, and a material feed pipe allowing the outside and the inside of the container structure to communicate with each other. In the heating block, as a flow path in which the material to be heated flows, a main header pipe connected to the material feed pipe and extending in the horizontally, and a riser pipe branching from the main header pipe and extending vertically are formed. As a condensation path in which the working fluid is cooled and condensed, condensation holes formed respectively on the opposite sides of the riser pipe and extending horizontally, and a condensation pit formed under the riser pipe are formed. Between the condensation holes and the condensation pit, the main header pipe is placed.Type: ApplicationFiled: April 11, 2008Publication date: February 24, 2011Applicants: National University Corporation Tohoku University, Toshiba Mitsubishi-Electric Indus. Sys. Corp.Inventors: Tadahiro Ohmi, Masafumi Kitano, Hisaaki Yamakage, Yoshihito Yamada
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Publication number: 20110018577Abstract: There is provided a wafer on which a plurality of electronic devices and circuits under test are to be formed, where each circuit under test includes a plurality of transistors under measurement provided in electrically parallel, a selecting section which sequentially selects the respective transistors under measurement, and an output section which sequentially outputs the source voltages of the transistors under measurement sequentially selected by the selecting section.Type: ApplicationFiled: October 7, 2010Publication date: January 27, 2011Applicant: NATIONAL UNIVERSITY CORPORATION TOHOKU UNIVERSITYInventors: SHIGETOSHI SUGAWA, AKINOBU TERAMOTO
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Publication number: 20110000533Abstract: It is possible to reduce the contact resistance so as to improve the conversion efficiency of a photoelectric conversion element structure. Provided is a photoelectric conversion element structure of the pin structure which selects an upper limit energy level of the valence band of the p-type semiconductor or the electron affinity of the n-type semiconductor layer and the work function of a metal layer which is brought into contact with the semiconductor, so as to reduce the contact resistance as compared to the case when Al or Ag is used as an electrode. The selected metal layer may be arranged between the electrode formed from Al or Ag and the semiconductor or may be substituted for the n- or p-type semiconductor.Type: ApplicationFiled: March 2, 2009Publication date: January 6, 2011Applicants: NATIONAL UNIVERSITY CORPORATION TOHOKU UNIVERSITY, TOKYO ELECTRON LIMITEDInventors: Tadahiro Ohmi, Tetsuya Goto, Kouji Tanaka, Yuichi Sano
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Publication number: 20110000783Abstract: Provided is a rotary magnet sputtering apparatus which includes a plasma shielding member and an outer wall connected to the ground and which has a series resonant circuit and a parallel resonant circuit between the plasma shielding member and the outer wall. The series resonant circuit has a very low impedance only at its resonant frequency while the parallel resonant circuit has a very high impedance only at its resonant frequency. With this configuration, the impedance between substrate RF power and the plasma shielding member becomes very high so that it is possible to suppress the generation of plasma between a substrate 10 to be processed and the plasma shielding member. Further, since a series resonant circuit is provided between a target and the ground, the RF power is efficiently supplied only to a region where the substrate passes under the target, so that a self-bias voltage is generated.Type: ApplicationFiled: March 2, 2009Publication date: January 6, 2011Applicants: NATIONAL UNIVERSITY CORPORATION TOHOKU UNIVERSITY, TOKYO ELECTRON LIMITEDInventors: Tadahiro Ohmi, Tetsuya Goto, Takaaki Matsuoka
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Patent number: 7863925Abstract: There is provided a wafer on which a plurality of electronic devices and circuits under test are to be formed, where each circuit under test includes a plurality of transistors under measurement provided in electrically parallel, a selecting section which sequentially selects the respective transistors under measurement, and an output section which sequentially outputs the source voltages of the transistors under measurement sequentially selected by the selecting section.Type: GrantFiled: September 19, 2007Date of Patent: January 4, 2011Assignee: National University Corporation Tohoku UniversityInventors: Shigetoshi Sugawa, Akinobu Teramoto
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Publication number: 20100330390Abstract: A structural member for a manufacturing apparatus has a metal base member mainly composed of aluminum, a high-purity aluminum film formed on the surface of the metal base member, and a nonporous amorphous aluminum oxide passivation film which is formed by anodizing the high-purity aluminum film. A method for producing a structural member for a manufacturing apparatus, includes forming a high-purity aluminum film on the surface of a metal base member mainly composed of aluminum, and anodizing the high-purity aluminum film in a chemical conversion liquid having a pH of 4-10 and containing a nonaqueous solvent, which has a dielectric constant lower than that of water and dissolves water, thereby converting at least a surface portion of the high-purity aluminum film into a nonporous amorphous aluminum oxide passivation film.Type: ApplicationFiled: December 21, 2007Publication date: December 30, 2010Applicants: NATIONAL UNIVERSITY CORPORATION TOHOKU UNIVERSITY, MITSUBISHI CHEMICAL CORPORATIONInventors: Tadahiro Ohmi, Minoru Tahara, Yasuhiro Kawase
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Publication number: 20100308839Abstract: An electronic device that includes an actual operation circuit that operates during an actual operation of the electronic device, a second test circuit and a third test circuit that operate during a test of the electronic device, and a power supply section. The power supply section, during the actual operation of the electronic device, does not apply a power supply voltage to the second test circuit and applies power supply voltages to the actual operation circuit and the third test circuit. The power supply section, to obtain identification of the electronic device, applies a power supply voltage to the second test circuit.Type: ApplicationFiled: August 18, 2010Publication date: December 9, 2010Applicants: NATIONAL UNIVERSITY CORPORATION TOHOKU UNIVERSITY, ADVANTEST CORPORATIONInventors: Toshiyuki Okayasu, Shigetoshi Sugawa, Akinobu Teramoto
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Patent number: 7848828Abstract: Provided is a method for managing manufacturing apparatuses used in a managed production line including a plurality of manufacturing processes for manufacturing an electronic device, each of the apparatuses being used in one or more of the processes. The method includes acquiring a property of a reference device manufactured in a predetermined reference production line including the manufacturing processes to be performed, performing at least one of the manufacturing processes in the managed production line, performing the other manufacturing processes in the reference production line, and manufacturing a comparison device. The method further includes measuring a property of the comparison device, comparing the measured properties of the reference and the comparison devices, and judging whether a manufacturing apparatus used in the at least one manufacturing process in the managed production line is defective or not, based on a property difference between the reference and the comparison devices.Type: GrantFiled: March 25, 2008Date of Patent: December 7, 2010Assignees: National University Corporation Tohoku University, Advantest CorporationInventors: Toshiyuki Okayasu, Shigetoshi Sugawa, Akinobu Teramoto
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Publication number: 20100288439Abstract: A disclosed top plate that is configured as a solid part and provided in an opening in a ceiling portion of a plasma process chamber whose inside is evacuatable to vacuum includes plural gas conduits formed in a horizontal direction of the top plate; and gas ejection holes that are open in a first surface of the top plate, the first surface facing the inside of the plasma process chamber and in gaseous communication with the plural gas conduits.Type: ApplicationFiled: August 21, 2008Publication date: November 18, 2010Applicants: TOKYO ELECTRON LIMITED, NATIONAL UNIVERSITY CORPORATION TOHOKU UNIVERSITYInventors: Kiyotaka Ishibashi, Tadahiro Ohmi, Tetsuya Goto, Masahiro Okesaku
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Patent number: 7820467Abstract: A solid-state imaging device, a line sensor and an optical sensor for enhancing a wide dynamic range while keeping high sensitivity with a high S/N ratio, and a method of operating a solid-state imaging device for enhancing a wide dynamic range while keeping high sensitivity with a high S/N ratio are provided. The solid-state imaging device comprises an integrated array of a plurality of pixels, each of which comprises a photodiode PD for receiving light and generating photoelectric charges, a transfer transistor Tr1 for transferring the photoelectric charges, and a storage capacitor element C connected to the photodiode PD at least through the transfer transistor Tr1 for accumulating, at least through the transfer transistor Tr1, the photoelectric charge overflowing from the photodiode PD during accumulating operation.Type: GrantFiled: March 4, 2009Date of Patent: October 26, 2010Assignee: National University Corporation Tohoku UniversityInventor: Shigetoshi Sugawa
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Patent number: 7812595Abstract: There is provided a device identifying method for identifying an electronic device including therein an actual operation circuit and a test circuit having a plurality of test elements provided therein, where the actual operation circuit operates during an actual operation of the electronic device and the test circuit operates during a test of the electronic device.Type: GrantFiled: February 18, 2008Date of Patent: October 12, 2010Assignees: National University Corporation Tohoku University, Advantest CorporationInventors: Toshiyuki Okayasu, Shigetoshi Sugawa, Akinobu Teramoto
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Patent number: 7800673Abstract: A solid-state imaging device and an optical sensor, which can enhance a wide dynamic range while keeping a high sensitivity with a high S/N ratio, and a method of operating a solid-state imaging device for enhancing a wide dynamic range while keeping a high sensitivity with a high S/N ratio are disclosed. An array of integrated pixels has a structure wherein each pixel comprises a photodiode PD for receiving light and generating and accumulating photoelectric charges and a storage capacitor element CS coupled to the photodiode PD through a transfer transistor Tr1 for accumulating the photoelectric charges overflowing from the photodiode PD. The storage capacitor element CS is structured to accumulate the photoelectric charges overflowing from the photodiode PD in a storage-capacitor-element accumulation period TCS that is set to be a period at a predetermined ratio with respect to an accumulation period of the photodiode PD.Type: GrantFiled: April 12, 2005Date of Patent: September 21, 2010Assignee: National University Corporation Tohoku UniversityInventors: Shigetoshi Sugawa, Satoru Adachi, Kyoichi Yahata, Tatsuya Terada
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Publication number: 20100233876Abstract: In a film forming method, a substrate is first loaded into a vacuum-evacuable processing chamber. At least a transition metal-containing source gas and a reduction gas are supplied into the processing chamber, and the substrate is heated. Then, a thin film is formed in a recess in the surface of the substrate by heat treatment. Accordingly, the surface recess of the substrate can be filled with a copper film.Type: ApplicationFiled: June 8, 2007Publication date: September 16, 2010Applicants: TOKYO ELECTRON LIMITED, NATIONAL UNIVERSITY CORPORATION TOHOKU UNIVERSITYInventors: Kenji Matsumoto, Junichi Koike, Koji Neishi
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Publication number: 20100230387Abstract: Occurrence of a back-flow of plasma or ignition of gas for plasma excitation in a longitudinal hole portion can be prevented more completely, and a shower plate in which efficient plasma excitation is possible is provided. In shower plate 105, which is arranged in processing chamber 102 of a plasma processing apparatus and discharges gas for plasma excitation into processing chamber, porous-gas passing body 114 having a pore that communicates in the gas flow direction is fixed onto longitudinal hole 112 used as a discharging path of gas for plasma excitation. The pore diameter of a narrow path in a gas flowing path formed of a pore, which communicates to porous-gas passing body 114, is 10 ?m or lower.Type: ApplicationFiled: June 13, 2007Publication date: September 16, 2010Applicants: TOKYO ELECTRON LIMITED, NATIONAL UNIVERSITY CORPORATION TOHOKU UNIVERSITYInventors: Masahiro Okesaku, Tetsuya Goto, Tadahiro Ohmi, Kiyotaka Ishibashi
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Publication number: 20100216300Abstract: A semiconductor device manufacturing method, the method including: forming a semiconductor element on a semiconductor substrate; and by using microwaves as a plasma source, forming an insulation film on the semiconductor element by performing a CVD process using microwave plasma having an electron temperature of plasma lower than 1.5 eV and an electron density of plasma higher than 1×1011 cm?3 near a surface of the semiconductor substrate.Type: ApplicationFiled: August 7, 2008Publication date: August 26, 2010Applicants: TOKYO ELECTRON LIMITED, NATIONAL UNIVERSITY CORPORATION TOHOKU UNIVERSITYInventors: Hirokazu Ueda, Toshihisa Nozawa, Takaaki Matsuoka, Akinobu Teramoto, Tadahiro Ohmi
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Publication number: 20100193900Abstract: A base is formed of a material, such as SiC, having mechanical characteristics higher than those of silicon for forming a semiconductor layer, and the base and the semiconductor layer are bonded through an insulating layer. After bonding, an SOI substrate is formed by mechanically separating the semiconductor layer from the base, and the separated semiconductor layer is reused for forming the subsequent SOI substrate. Thus, a large SOI substrate having a diameter of 400 mm or more, which has been difficult to obtain by conventional methods, can be obtained.Type: ApplicationFiled: February 25, 2008Publication date: August 5, 2010Applicant: NATIONAL UNIVERSITY CORPORATION TOHOKU UNIVERSITYInventors: Tadahiro Ohmi, Akinobu Teramoto, Sumio Sano, Makoto Yoshimi
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Publication number: 20100178775Abstract: A shower plate is disposed in a processing chamber in a plasma processing apparatus, and plasma excitation gas is released into the processing chamber so as to generate plasma. A ceramic member having a plurality of gas release holes having a diameter of 20 ?m to 70 ?m, and/or a porous gas-communicating body having pores having a maximum diameter of not more than 75 ?m communicating in the gas-communicating direction are sintered and bonded integrally with the inside of each of a plurality of vertical holes which act as release paths for the plasma excitation gas.Type: ApplicationFiled: September 26, 2007Publication date: July 15, 2010Applicants: TOKYO ELECTRON LIMITED, NATIONAL UNIVERSITY CORPORATION TOHOKU UNIVERSITYInventors: Masahiro Okesaku, Tadahiro Ohmi, Tetsuya Goto, Takaaki Matsuoka, Toshihisa Nozawa, Atsutoshi Inokuchi, Kiyotaka Ishibashi
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Publication number: 20100139775Abstract: A pressure type flow control device enabling a reduction in size and an installation cost by accurately controlling the flow of a fluid in a wide flow range. Specifically, the flow of the fluid flowing in an orifice (8) is calculated as Qc=KP1 (K is a proportionality factor) or Qc=KP2m(P1?P2)n (K is a proportionality factor and m and n are constants) by using a pressure P1 on the upstream side of the orifice and a pressure P2 on the downstream side of the orifice. A fluid passage between the downstream side of the control valve of the flow control device and a fluid feed pipe is formed of at least two or more fluid passages positioned parallel with each other. Orifices with different fluid flow characteristics are interposed in the fluid passages positioned parallel with each other. For the control of the fluid in a small flow area, the fluid in the small flow area is allowed to flow to one orifice.Type: ApplicationFiled: June 22, 2006Publication date: June 10, 2010Applicants: FUJIKIN INCORPORATED, NATIONAL UNIVERSITY CORPORATION TOHOKU UNIVERSITY, TOKYO ELECTRON LTD.Inventors: Tadahiro Ohmi, Masahito Saito, Shoichi Hino, Tsuyoshi Shimazu, Kazuyuki Miura, Kouji Nishino, Masaaki Nagase, Katsuyuki Sugita, Kaoru Hirata, Ryousuke Dohi, Takashi Hirose, Tsutomu Shinohara, Nobukazu Ikeda, Tomokazu Imai, Toshihide Yoshida, Hisashi Tanaka
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Publication number: 20100126852Abstract: In a rotary magnet sputtering apparatus, a target consumption displacement quantity is measured, and corresponding to the measurement results, a distance between a rotating magnet group and a target is adjusted, and uniform film forming rate is achieved over a long period of time so as to reduce the change of a target surface due to consumption of the target and to reduce the change of the film forming rate with time. An ultrasonic sensor or a laser transmitting/receiving device may be used as a means for measuring the consumption displacement quantity of the target.Type: ApplicationFiled: March 28, 2008Publication date: May 27, 2010Applicants: NATIONAL UNIVERSITY CORPORATION TOHOKU UNIVERSITY, TOKYO ELECTRON LIMITEDInventors: Tadahiro Ohmi, Tetsuya Goto, Takaaki Matsuoka
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Publication number: 20100101945Abstract: In a magnetron sputtering apparatus configured such that a magnetic field pattern on a target surface moves with time by means of a rotary magnet group, an object of this invention is to solve a problem that the failure rate of substrates to be processed becomes high upon plasma ignition or extinction, thereby providing a magnetron sputtering apparatus in which the failure rate of the substrates is smaller than conventional. In a magnetron sputtering apparatus of this invention, a plasma shielding member having a slit is disposed on an opposite side of a target with respect to a rotary magnet group. The distance between the plasma shielding member and a psubstrate to be processed is set shorter than the electron mean free path or the sheath width. Further, the width and the length of the slit are controlled to prevent impingement of plasma on the processing substrate. This makes it possible to reduce the failure rate of the substrates.Type: ApplicationFiled: March 14, 2008Publication date: April 29, 2010Applicants: NATIONAL UNIVERSITY CORPORATION TOHOKU UNIVERSITY, TOKYO ELECTRON LIMITEDInventors: Tadahiro Ohmi, Tetsuya Goto, Takaaki Matsuoka