Abstract: A first conductive layer is formed on the bottom surface of a substrate, including a bottom section, a step and a side wall, and a light emitting device is mounted on the first conductive layer. A second conductive layer is formed on the step, and is electrically connected to the fight emitting device. The substrate is filled with a translucent resin. A third and fourth conductive layers, which are insulated from each other, are formed on a cap in the form of plate which is attached to an opening of the substrate. A photodetector facing the light emitting device is mounted on the third conductive layer, thereby the light emitting device and the fourth conductive layer are electrically connected with each other. The conductive layers are respectively connected to external electrodes, which are formed on the external surface of the substrate, via through holes formed through the substrate.

Abstract: A method of manufacturing semiconductor packaging according to the present invention includes a first step of mounting a component on a heat spreader with high melting point solder, and a second step of adhering a frame, which is formed separate from the heat spreader, upon the heat spreader so as to surround the component following completion of the first step.

Abstract: In a high-frequency variable attenuator for variably attenuating an input high-frequency signal in response to a control voltage to produce an output high-frequency signal, a reference voltage generating circuit generates a controllable reference voltage in response to the control voltage. Connected to the reference voltage generating circuit, an attenuating circuit attenuates the input high-frequency signal on the basis of the control voltage in reference with the controllable reference voltage to produce the output high-frequency signal.

Abstract: A method for forming a self-aligned bipolar transistor includes the steps of combination etching a silicon substrate in an opening to form a concave surface on the silicon substrate, and forming an intrinsic base and an associated emitter on the concave surface. The combination etching includes an isotropic etching and subsequent wet etching. The concave surface increases the distance between the external base for the intrinsic base and the emitter to thereby increase the emitter-base breakdown voltage.

Abstract: A 180° phase shift circuit includes a balun having an unbalanced port and a pair of balanced ports, a pair of impedance matching lines each connected between one of the pair of balanced ports and one of a pair of balanced signal terminals, and a &lgr;g/2 distributed parameter line having ends each connected via a resistor to a node connecting together corresponding impedance matching line and corresponding balanced signal terminal.

Abstract: A heterojunction bipolartansistor is fabricated on a semi-insulating substrate, and has a mesa structure, wherein an emitter signal line of titanium-platinum-gold alloy is held in contact with the collector layer as well as the emitter layer for forming a Schottky barrier diode connected between the emitter and the collector so that surge current flows before damage of the p-n junction of the heterojunction bipolar transistor.

Abstract: There is provided a method of fabricating a semiconductor device, including the steps of (a) forming a first conductivity type base region in a second conductivity type collector region by molecular beam epitaxy (MBE), (b) forming an emitter region in the base region by implanting second conductivity type impurities into the base region by MBE; (c) forming a second conductivity type amorphous layer on the emitter region by MBE, and (d) forming an emitter contact region by causing the second conductivity type amorphous layer to grow in solid phase. The method makes it possible to establish not only a base region but also an emitter region in ambient temperature growth by means of an MBE apparatus. Herein, the emitter region has a shallow depth and uniform impurities content by implanting antimony (Sb) into a region with a substrate being applied a voltage directly in an MBE apparatus.

Abstract: A semiconductor device includes (a) a printed wiring board, (b) a semiconductor chip mounted on the printed wiring board, (c) a molded resin formed on the printed wiring board, covering the semiconductor chip therewith, and (d) at least one metal wiring formed on the printed wiring board and extending externally beyond the molded resin. The metal wiring is plated with a metal having a small adhesion force with the molded resin. An interfacial surface between the metal and the molded resin acts as a path through which moisture contained in the semiconductor device escapes outside when the semiconductor device is heated.

Abstract: A variable gain type amplifier includes a first amplifying circuit, an attenuating circuit connected to an output of the first amplifying circuit, and a second amplifying circuit connected to an output of the first amplifying circuit. An amplification of the first amplifying circuit is adjusted based on a control voltage, and an attenuation of the attenuating circuit is adjusted based on the control voltage.

Abstract: A differential amplifier which provides a precise phase difference of 180 degrees between a pair of differential output signals and which has low power consumption. The differential amplifier comprises a differential amplifying stage which has a differential pair of transistors. An unbalanced input signal is applied to the control electrode of one of the transistors and a pair of differential signals are outputted from a pair of output nodes of the differential amplifying stage. The differential amplifier also has a signal delay element, coupled between the output node on the side of the transistor to which the unbalanced input signal is applied and an output terminal of the differential amplifier, for compensating the phase difference. The signal delay element may have a plurality of taps for precisely adjusting the phase difference.

Abstract: An active bias circuit having a combined configuration of the Wilson and Widlar current source configurations is provided, which makes it possible to set the output bias voltage at approximately zero (OV) even if a reference voltage applied to generate a reference current does not reach OV. This circuit comprises cascode-connected first and second transistors cascode-connected third and fourth transistors, and a resistor with a specific voltage drop generated by a current flowing through the same. The absolute value of the output bias voltage is decreased by the value of the voltage drop of the resistor compared with the case where the resistor is not provided. The resistor is provided between the gates/bases of the first and third transistors, or between the gate/base and source/emitter of the fourth transistor.

Abstract: Lower metal wiring is formed on a base insulating film. A BCB film which is formed of a BCB (benzocyclobutene) resin is formed on the base insulating film and metal wiring. A SiO2 film is formed on the BCB film. A resist film is formed on the SiO2 film, and patterned using a lithography technique. The SiO2 film is etched using the resist film as a mask. The BCB film is anisotropically etched with a mixture of Cl2/BCl3/O2 using the SiO2 film as a mask, thereby to form a contact hole. The contact hole is filled with a conductor, thereby forming upper metal wiring.

Abstract: A semiconductor apparatus comprising: a semiconductor substrate; a first surface of the semiconductor substrate on which a semiconductor device is formed; a second surface opposite to the first surface of the semiconductor substrate; a via hole penetrating through the semiconductor substrate from the first surface to second surface; an electrode, provided on the second surface, connecting to the via hole; wherein the electrode having a barrier layer for preventing any diffusion of a soldering material into the via hole.

Abstract: The variable gain amplifier includes a parallel connection of resistance R2 and capacitor C2. Resistance R2 may be replaced by inductance L, and bipolar transistors may be replaced by other types such MOS transistors. Resistance R2 gives a current feedback for transistor Q2, thereby lowering the mutual conductance “gm” of transistor Q2, and limiting the current flowing from voltage supply V0. The emitter area ratio (the emitter area of transistor Q2: the emitter area of Q3) made to be 1: n where “n” is greater than or equal to 1, thereby controlling each current. Capacitor C2 is connected in parallel with R2 connected with the base of transistor Q2 is a bypass capacitor for lowering the impedance of the base of transistor Q2 in higher frequency range. Capacitor C2 is a peaking capacitor, because it improves the high frequency characteristics.

Abstract: The present invention provides a bonding structure between a bonding pad and a bonding portion of a bonding wire made of an Au-base material, wherein said bonding pad further comprises: a base layer; at least a barrier layer overlying said base layer; and a bonding layer overlying said at least barrier layer, said bonding layer including an Al-base material, and wherein said bonding portion of said bonding wire is buried in said bonding layer, and an Au—Al alloy layer extends on an interface between said bonding portion and said bonding layer, and a bottom of said Au—Al alloy layer is in contact with or adjacent to an upper surface of said barrier layer.

Abstract: A heterojunction bipolar transistor and a protective PIN diode are implemented by two multi-layered compound semiconductor structures epitaxially grown on respective regions of a semi-insulating substrate; the entire upper surface of the base layer is covered with the emitter layer, and the base electrode on the emitter layer projects through the emitter layer into the base layer; although the two multi-layered compound semiconductor structures are covered with a passivation layer, the emitter layer prevents the base layer from direct contact with the passivation layer so that leakage current hardly flows between the base and the emitter.

Abstract: A semiconductor package has a base member made of a wiring board or a lead frame, a wall member fixed onto the base member to define a cavity, and a cured-resin cap member for encapsulating a semiconductor chip in the cavity. The curable-resin cap member is fixed onto the wall member by the curing process for the curable-resin cap member.

Abstract: In a predistortion type linearizer including a FET, an input matching circuit connected to the drain of the FET for receiving an input signal, an output matching circuit connected to the source of said the FET for outputting an output signal, and a inductor having a first terminal connected to the gate of the 1 FET and a second terminal for receiving a first control voltage, a variable impedance circuit is connected to the second terminal of the inductor, and the impedance of the variable impedance circuit is adjusted by a second control voltage.

Abstract: A field effect transistor includes a semiconductor substrate with a channel layer being formed on its surface, a source electrode and a drain electrode formed at a distance on said semiconductor substrate, and a gate electrode placed between the source electrode and the drain electrode and making a Schottky junction with the channel layer. The gate electrode is provided with an overhanging field plate section and between the field plate section and the channel layer, there is laid a dielectric film. When the relative permittivity and the film thickness of the dielectric film are denoted by ∈ and t (nm), respectively, the following condition is satisfied 5≦∈<8, and 100<t<350.