Abstract: A semiconductor package comprises a semiconductor chip, an interposer substrate, a plurality of unfilled end face through holes arrayed at the periphery of the semiconductor package, a plurality of inner through holes, a plurality of end face through hole electrodes each formed inside the end face through holes so as to be exposed on a side face of the semiconductor package and a plurality of inner electrodes each formed around openings of the inner through holes on the other side of the interposer substrate, the semiconductor chip being mounted on one side of the interposer substrate, the electrodes being laid out in an array on the other side of the interposer substrate.

Abstract: There is provided a semiconductor laser comprising an n-InP substrate 1; a multilayer film including a strained MQW active layer 6 on the n-InP substrate 1; a p-electrode 18 on the multilayer film; a pair of grooves 15 separating the multilayer film in both edges of the p-electrode 18 and extending to the n-InP substrate 1; and a plurality of diffraction gratings formed in an area from one to the other of the pair of grooves 15 in a diffraction grating forming surface formed in the upper surface of the n-InP substrate 1 or the upper surface of any of the semiconductor films in the multilayer film.

Abstract: A package includes: a substrate having a ridged peripheral portion and a center portion defined by and lower in level than the ridged peripheral portion. A semiconductor chip is mounted on the center portion. A plurality of lead is electrically coupled to the semiconductor chip and penetrates the substrate outwardly from the center portion. The package also includes a cap defining a cavity space which accommodates the semiconductor chip. The cap has a cap bonding face bonded with a substrate bonding face of the ridged peripheral portion. The cap bonding face and the substrate bonding face are higher in level than the center portion.

Abstract: A photoelectric current and voltage converting circuit converts a photo current Ipd generated by the input to photo diode into a voltage Va by a feedback resistor connected to an inverting input and an output of an amplifier, and compares the output voltage Va with a threshold voltage Vth from a reference voltage circuit to output a binary signal. Divided voltage Vb gained from a connecting node of the feedback resistors is inputted to a non-inverting input of the reference voltage circuit and is offset to a higher voltage by Vos to generate a threshold voltage Vth. As a result, the threshold voltage Vth can be supplied which impedance is low and robust to noise, and errors of the comparator or jitter of the output of the comparator are suppressed.

Abstract: A lid-member holder is used to define envelopers encapsulating electronic components in production of hollow-package type electronic products. A plurality of lid members are temporarily held by the holder body. The lid members are arranged so as to be consistent with an arrangement of surrounding wall members, which are to be sealed with the lid members in a lump to define the envelopers, and the temporary holding of the lid members by the holder body is realized such that lid members can be separated from the lid members after the surrounding wall members are completely sealed with the lid members, without the lid members being removed from the surrounding wall members.

Abstract: A photoelectric current and voltage converting circuit includes a light receiving element, an amplifier, a feedback resistor, an offset resistor, a constant current source, and a comparator. A feedback resistor is connected between the input and the output of the amplifier and converts photo current into voltage. An terminal of the offset resistor is connected to the output of the amplifier. The constant current source is connected to another terminal of the offset resistor. The comparator compares the connected point of the offset resistor and the constant current source with a reference voltage and outputs a binary signal. The reference voltage is an input voltage of the amplifier or the divided voltage of the intermediate point of the feedback resistor.

Abstract: This invention provides a method and an apparatus of measuring a micro-structure, capable of evaluating a geometry of a micro-structure formed typically on the surface of a semiconductor substrate, in a non-destructive, easy, precise and quantitative manner. A reflection spectrum of a sample having a known dimension of a target micro-geometry is measured (A1), features (waveform parameters) which strongly correlate to a dimension of the measured micro-geometry are determined (A2), a relation between the dimension of the micro-geometry and the waveform parameters is found (A3), and a dimension of the micro-structure having an unknown dimension is finally determined using this relation and based on the reflection spectrum obtained therefrom (A4, A5).

Abstract: A PLL frequency synthesizer circuit integrated on a semiconductor integrated circuit, comprises a voltage-controlled oscillator circuit provided with a capacitor, an inductor, and a variable capacitor element for oscillating using the resonance frequencies of the capacitor and inductor, for outputting the oscillation frequency signal of a variable capacitor element, a negative feedback loop circuit configured to comprise the voltage-controlled oscillator circuit, capable of looping the signal output from the voltage-controlled oscillator circuit and performing a frequency acquisition operation for adjusting the frequency of the signal to a desired locking frequency, a tuning circuit for performing tuning so that the oscillation frequency approaches the locking frequency, by modulating the capacitance value of the capacitor of the voltage-controlled oscillator circuit prior to the frequency acquisition operation, and a reference potential application circuit for applying a reference potential to the variable c

Abstract: The phase locked loop frequency synthesizer, includes: an LC-tank circuit which includes an inductor and a variable capacitor in which the capacity changes depending on the input voltage; a group of fixed-value capacitors which is connected to the LC-tank circuit in parallel; a voltage control oscillating unit which outputs a signal with a frequency determined by the LC-tank circuit and the group of fixed-value capacitors; a phase control unit which generates an output current based on an error operator between a first signal with a divided frequency of a reference frequency and a second signal with a divided frequency of the frequency output from the voltage control oscillating unit; a fixed-value capacitor controlling unit which outputs a selection signal which determines the combination of the fixed-value capacitors to be connected to the LC-tank circuit in parallel based on a frequency dividing ratio setting signal including information about dividing ratio of the second signal, and controls the connectio

Abstract: A bias circuit which applies a bias voltage to a control terminal of a first active element for an RF signal amplification, includes a threshold voltage change compensation circuit and a first temperature compensation circuit. The threshold voltage change compensation circuit contains a second active element and compensates the bias voltage based on a change in threshold voltage of the first active element by using the second active element. The first temperature compensation circuit is connected between the control terminal and the voltage change compensation circuit and configured to compensate a change in the bias voltage based on a temperature change.

Abstract: A heterojunction bipolar transistor of the present invention is produced from a wafer including a substrate and a collector layer of a first conductivity type, a base layer of a second conductivity type and an emitter layer of the first conductivity type sequentially laminated on the substrate in this order. First, the wafer is etched up to a preselected depth of the collector layer via a first photoresist, which is formed at a preselected position on the emitter layer, serving as a mask. Subsequently, the collector layer etched with at least the sidewalls of the base layer and collector layer, which are exposed by the first etching step, and a second photoresist covering part of the surface of the collector layer contiguous with the sidewalls serving as a mask.

Abstract: A binary FSK modulator circuit is composed of a signal mapping circuit, a D/A converter circuit, and a quadrature modulator circuit. The signal mapping circuit generates I data and Q data through signal mapping in response to an input bit stream, the I data being representative of an I channel projection and the Q data being representative of a Q channel projection. The D/A converter circuit develops an I-channel signal and a Q-channel signal through implementing D/A conversion on the I data and the Q data, respectively. The quadrature modulator circuit develops a resultant FSK-modulated signal through quadrature modulation of the I-channel signal and the Q-channel signal on a carrier signal.

Abstract: A semiconductor device for optically coupling a semiconductor light-emitting device to an optical fiber, includes (a) a lens which focuses lights emitted from the semiconductor light-emitting device, onto the optical fiber, (b) a shell which supports the lens therewith, the shell being comprised of a cylindrical first portion, a second portion integral with the first portion at an upper end of the first portion and being formed centrally with an opening into which the lens is to be fit, and a cylindrical third portion extending from the first portion upwardly beyond the second portion, (c) glass arranged around the lens for keeping the lens and the opening hermetically sealed, and (d) a reinforcement formed on at least one of upper and lower surfaces of the second portion for preventing the shell from being deformed due to a stress acting on the shell.

Abstract: A semiconductor device includes a sub-collector layer, a collector layer, a base layer, an emitter layer, and an emitter cap layer, which are sequentially laminated on a substrate. It also includes an emitter electrode, a base electrode, and a collector electrode, which are respectively formed on the emitter cap layer, the base layer, and the sub-collector layer. The sub-collector layer is made up of a first sub-collector layer adjacent to the substrate and a second sub-collector layer adjacent to the collector layer. In the area between adjacent device elements, the first sub-collector layer has an element insulating region created by ion implantation, and the second sub-collector layer has a recess-shaped element insulating region.

Abstract: A semiconductor device includes a low resistance semiconductor substrate, a high resistance semiconductor layer formed on the substrate, an insulation layer formed on the semiconductor layer, and a transistor element composed of a collector region, abase region, and an emitter region formed in the semiconductor layer. The device further includes an emitter electrode formed in the insulation layer to be connected to the emitter region, a sub-emitter electrode formed in the insulation layer connected to the emitter electrode, a low resistance impurity-diffusion region formed in the semiconductor layer such that the sub-emitter electrode is connected to the substrate through the impurity-diffusion region, a base electrode formed in the insulation layer to be connected to the base region, and a base-bonding pad formed on the insulation layer to be connected to the base electrode.

Abstract: A heterojunction bipolar transistor, having a structure in which a subcollector layer of a first conductive type having a higher doping concentration than a collector layer, a collector layer of the first conductive type, a base layer of the second conductive type, and an emitter layer of the first conductive type are deposited, in order, on a semi-insulating semiconductor substrate, and in which a hole barrier layer of semiconductor material with a band gap wider than that of the base layer is inserted between the base layer and the collector layer, so as to be in direct contact with the base layer.

Abstract: A heterojunction bipolar transistor has a raised breakdown voltage and restrains the rising characteristic of IC-VCE characteristic from degrading. The collector region includes first, second, and third collector layers of semiconductor. The first collector layer is made of a doped or undoped semiconductor in such a way as to contact the sub-collector region. The second collector layer is made of a doped or undoped semiconductor having a narrower band gap than the first collector layer in such a way as to contact the base region. The third collector layer has a higher doping concentration than the second collector layer in such a way as to be located between or sandwiched by the first collector layer and the second collector layer.

Abstract: An optical semiconductor device includes a substrate and a plurality of optical parts mounted thereon. Guide grooves are formed in the substrate at the mounting positions of the optical parts. Each guide groove has first side surfaces, which are substantially orthogonal to the direction of the optical axis, second side surfaces, which are substantially parallel to the direction of the optical axis and substantially perpendicular to the surface of the substrate, and a bottom surface substantially parallel to the surface of the substrate. Each guide groove has a size and a depth that allow at least a bottom portion of the corresponding optical part to be received therein. The corresponding optical part is accommodated in each guide groove in abutting contact with the first side surfaces of the guide groove, whereby the optical parts are aligned with one another along the direction of the optical axis.

Abstract: A frequency synthesizer (100) that may have reduced spurious noise caused by a voltage controlled oscillator (VCO) (4) output sneaking into an input side of a phase comparison circuit (1) has been disclosed. A beat frequency component that may be generated by mixing of a portion of a VCO output sneaking into an input side of a phase comparison circuit (1) through a reference signal (REF) or a comparison signal (SIG) may be shifted to a high frequency region by providing a modulator circuit (7) on a reference signal side or a comparison signal side. Thus, a low pass filter circuit (3) may provide attenuation to the spurious noise. In this way, spurious noise in the VCO output may be reduced.

Abstract: In a photocurrent-to-voltage conversion apparatus for converting a photocurrent flowing through a light receiving element into a detection voltage, an amplifier, a feedback resistor and a clamping MOS transistor are provided. The amplifier has an input connected to the light receiving element and an output for generating the detection voltage, and includes (2n+1) inverter stages connected in series where n is 1, 2 . . . . The feedback resistor and the clamping transistor are connected between the output and input of the amplifier. The clamping MOS transistor is controlled by an output voltage of a non-final inverter one of the inverter stages.