Abstract: A semiconductor laser device includes an active layer and first and second current blocking layers having aligned stripe openings for injecting operating current into the active layer in a current injection area. The second current blocking layer has another opening, through which the first current blocking layer contacts an external cladding layer, in the vicinity of the emission facet of the laser cavity to form a current non-injection area. The first current blocking layer and the external cladding layer have a substantially equal refractive index.

Abstract: In a semiconductor switch apparatus including an input terminal, an output terminal, an AC ground terminal, a DC ground terminal, at least one series MOS transistor connected between the input terminal and the output terminal, and at least one shunt MOS transistor connected between one of the input terminal and the output terminal and the AC ground terminal, the series MOS transistor is formed within a first region of a semiconductor layer on a silicon-on-insulator configuration surrounded by a first trench insulating layer, and the shunt MOS transistor is formed within a second region of the semiconductor layer surrounded by a second trench insulating layer.

Abstract: An optical semiconductor device includes: an insulating base; and a lead structure which further includes: a flange supported on a first surface of the insulating base; at least a first type lead supported by the insulating base; at least an island for mounting at least an optical semiconductor element thereon, which is electrically connected to the at least first type lead; and at least a connection part extending between the at least island and the flange. The flange, the at least connection part, and the at least island comprise a single united part of the lead structure. The flange, the at least connection part, the at least island, and the at least first type lead comprise a same conductive material.

Abstract: In a gain-controlled amplifier, first, second and third transistors are provided, and a signal at one of input and output terminals is compared with a threshold voltage. When the compared signal is lower than the threshold, the second and third transistors are respectively turned into conducting and non-conducting states, and when the compared signal is higher than the threshold, the situation is in reverse. When the third transistor is non-conducting, the first and second transistors are configured to form a cascode amplifier between the input and output terminals to produce a low-noise, high-gain output signal. When the second transistor is non-conducting, the first and third transistors are configured so that the third transistor forms a base-grounded amplifier between the input and output terminals and the first transistor forms a diode for supplying a DC bias current to the third transistor to produce a low-distortion, low-gain output signal.

Abstract: A semiconductor device package includes a substrate, a semiconductor device formed on the substrate, a ground electrode formed on the substrate, a cover designed for covering the semiconductor device, and a tab unit extending from the cover and for holding the substrate. The cover has an outer surface made of conductive material and an inner surface made of insulation material, where the insulating inner surface faces the semiconductor device. The tab unit has a first contact surface which extends from the conductive outer surface and is contact with the ground electrode.

Abstract: A groove 34 having a generally U-shape cross section is formed in an N− type semiconductor layer 33 of an SOI substrate 30. A P− type well region 36 reaching a buried silicon oxide film 32 is formed in a surface layer on one side of the groove 34 and an N type well region 35 having substantially the same depth as that of the groove 34 is formed in the surface layer on the other side of the groove 34. A PN junction formed by the P− type well region 36 and the semiconductor layer 33 is formed in substantially coplanar with the side wall of the groove 34 on the side of the P− type well region 36. A P type base region 37 having substantially the same depth as that of the groove 34 and adjacent to the side wall of the groove 34 is formed in a surface layer of the P− type well region 36.

Abstract: A high-frequency circuit includes a bias circuit to which a gain control voltage is input and which controls gains of transistors arranged in the bias circuit in accordance with the gain control voltage, and a band-switching circuit which switches a band and through which a reference current runs. The band-switching circuit includes two transistors electrically connected in cascode to each other, one of the two transistors which is located downstream of the other has a gate electrically connected to a gain control voltage terminal through which the gain control voltage is input, and each of the two transistors is comprised of a complete enhancement mode field effect transistor. The bias circuit includes a pair of transistors and a band-switching transistor. The band-switching transistor is electrically connected in series to a line through which the gain control voltage is supplied, and the gain control voltage is applied to the pair of transistors through the band-switching circuit.

Abstract: A photovoltaic solid state relay has a light-emitting diode for emitting light in response to an electrical control signal. First and second photovoltaic devices are optically coupled to the light-emitting diode for converting the light to first and second voltages, respectively. First and second unipolar transistors are provided having first and second gate electrodes for respectively receiving the first and second voltages and jointly establishing a first current conducting path between output terminals to which a load circuit will be connected. A bipolar transistor is provided having a base connected to a junction between the first and second unipolar transistors for establishing a second current conducting path in parallel to the first current conducting path in one of opposite directions depending on voltages applied to the output terminals.

Abstract: A recess for fully receiving an electronic component and a window opened from the bottom of the recess to the bottom surface of a metal substrate are formed in the metal substrate. A wiring board is bonded to the underside of the metal substrate, and the electronic component is fixed to the bottom of the recess. Input and output terminals of the electronic component are connected to electrode pads of the wiring board exposed within the window using wire bonding. A metal lid is bonded to the top surface of the metal substrate to close the opening of the recess. Electromagnetic waves generated by the electronic component are confined to the electronic device because the electronic device is surrounded by the metal substrate, the metal lid, and a ground electrode disposed on the wiring board. Heat dissipation performance is assured because the electronic component is connected to the metal substrate.

Abstract: A switching device for switching a plurality of RF signal lines to deliver a selected one of the RF signals to a receiver has an isolation D/U characteristic as high as 40 dB or higher. The switching device includes a mounting board made of dielectric and a matrix switch mounted thereon and implemented by one or more of SWIC. The RF signal lines in the switching device has no crossing point therebetween on either side of the mounting board to achieve the high isolation D/U ratio or lower cross-talk.

Abstract: In a semiconductor device having a semiconductor substrate, an internal electrode layer is formed on the semiconductor substrate. A barrier metal layer is formed on the internal electrode. An external electrode layer is formed on the barrier metal layer. A pad electrode is made of the internal electrode layer, the barrier metal layer, and the external electrode layer. A wire is electrically connected to the pad electrode. An area of the external electrode layer is set midway between an area of a polymerization portion of the wire on the pad electrode and a planar area of the barrier metal layer.

Abstract: In a photocurrent-to-binary signal conversion apparatus, a light receiving element receives a light signal so that a photocurrent in response to the light signal flows through the light receiving element. An amplifier converts the photocurrent into a detection voltage. A reference voltage generating circuit offsets the detection voltage on the side of the detection voltage to generate a reference voltage. A comparator compares the detection voltage with the reference voltage to generate a binary signal in accordance with whether or not the detection voltage is higher than the reference voltage.

Abstract: A field effect transistor includes: a source electrode and a drain electrode formed above a semiconductor active layer; an insulating film formed between the source electrode and the drain electrode above the semiconductor active layer so as to have an opening in which its side wall on a drain electrode side includes a tapered portion formed so as to be inclined from a plane perpendicular to an upper surface of the semiconductor active layer toward the drain electrode; and a gate electrode contacted to the semiconductor active layer through the opening so as to cover at least the side wall on the drain electrode side. Thus, there is provided the field effect transistor which has high breakdown voltage and high linear gain characteristics.

Abstract: A unit for stabilizing a wavelength of a light, includes (a) a first light-receiver directly receiving a part of laser beams irradiated from a semiconductor laser, (b) a wavelength-filter directly receiving a part of the laser beams, and having a transmittance varying in accordance with a wavelength of the received laser beams, and (c) a second light-receiver receiving laser beams having passed through the wavelength-filter, wherein the first light-receiver has a first edge, and the second light-receiver has a second edge located in the vicinity of the first edge, and the first edge has a first linear portion and the second edge has a second linear portion extending in parallel with the first linear portion.

Abstract: A single-phase clock CLK0 is divided into a clock signal CLK1 to drive nMOS transistor and a clock signal CLK2 to drive pMOS transistor, and the resulting clock signals are inputted to DFF circuits 1 to 3 constituting a frequency dividing circuit, making gms of nMOS and pMOS transistors larger than that could be achieved using the conventional technique. Therefore, frequency dividing performance can be greatly improved in comparison with that achieved using conventional technology.

Abstract: A photovoltaic solid state relay has a light-emitting diode for emitting light in response to an electrical control signal. First and second photovoltaic devices are optically coupled to the light-emitting diode for converting the light to first and second voltages, respectively. First and second unipolar transistors are provided having first and second gate electrodes for respectively receiving the first and second voltages and jointly establishing a first current conducting path between output terminals to which a load circuit will be connected. A bipolar transistor is provided having a base connected to a junction between the first and second unipolar transistors for establishing a second current conducting path in parallel to the first current conducting path in one of opposite directions depending on voltages applied to the output terminals.

Abstract: In a heterojunction field effect type semiconductor device, a channel layer is formed over a GaAs substrate, and a first semiconductor layer including no aluminum is formed over the channel layer. First and second cap layers of a first conductivity type are formed on the first semiconductor layer, to create a recess on the first semiconductor layer. First and second ohmic electrodes are formed on the first and second cap layers, respectively. A second semiconductor layer of a second conductivity type is formed on the first semiconductor layer within the recess, and the semiconductor layer is isolated from the first and second cap layers. A gate electrode is formed on the second semiconductor layer.

Abstract: A laser module comprises a laser diode secured on a semiconductor substrate for emission of a forward laser beam from its front end and a backward laser beam from a point source on its rear end in a horizontal direction. A photodiode, also secured on the substrate, has a light receiving surface extending in the horizontal direction by length L from an edge proximate to the laser diode for receiving a lower half of the backward laser beam, the light receiving surface being lower than the point source by a vertical distance Y, the edge being spaced a horizontal distance Z from the point source of the laser diode, wherein the horizontal distance Z is equal to or greater than (Y/tan &thgr;)−L, where &thgr; is a vertical angle in which the lower half of the backward laser beam radiates from the point source.

Abstract: This invention discloses a method and apparatus where a pre-treatment which reduce interfacial level density is carried out before thin film deposition on a substrate utilizing a catalytic gas phase reaction. The catalytic gas phase reaction is generated with a treatment gas which is supplied with the substrate via a thermal catalysis body provided near the substrate surface. Thin film deposition on the substrate surface is carried out after this pre-treatment. The thermal catalysis body is made of tungsten, molybdenum, tantalum, titanium or vanadium, and is heated by a heater. And, this invention also discloses a semiconductor device having a semiconductor-insulator junction with its interfacial level density is 1012 eV −1cm−2 or less, which is brought by the above pre-treatment in the insulator film deposition process.

Abstract: In a predistortion type linearizer including a FET, an input matching circuit connected to the drain of the FET for receiving an input signal, an output matching circuit connected to the source of said the FET for outputting an output signal, and a inductor having a first terminal connected to the gate of the FET and a second terminal for receiving a first control voltage, a variable impedance circuit is connected to the second terminal of the inductor, and the impedance of the variable impedance circuit is adjusted by a second control voltage.