Patents Assigned to NEC Compound Semiconductor Devices, Ltd.
  • Publication number: 20030209465
    Abstract: A package includes: a substrate having a ridged peripheral portion and a center portion defined by and lower in level than the ridged peripheral portion. A semiconductor chip is mounted on the center portion. A plurality of lead is electrically coupled to the semiconductor chip and penetrates the substrate outwardly from the center portion. The package also includes a cap deeming a cavity space which accommodates the semiconductor chip. The cap has a cap bonding face bonded with a substrate bonding face of the ridged peripheral portion. The cap bonding face and the substrate bonding face are higher in level than the center portion.
    Type: Application
    Filed: May 7, 2002
    Publication date: November 13, 2003
    Applicant: NEC COMPOUND SEMICONDUCTOR DEVICES, LTD
    Inventor: Hiroyuki Shoji
  • Publication number: 20030201113
    Abstract: A semiconductor device includes an insulating substrate having a first main face which is sealed with a sealing material and at least a set of input and output electrode patterns provided on the first main face. The input and output electrode patterns are separated from each other. The device also includes at least a ground electrode pattern having a ground potential. The ground electrode pattern is separated from the input and output electrode patterns. The device further includes at least an electrically conductive pattern extending over an inter-region between the input and output electrode patterns. The electrically conductive pattern is separated from the input and output electrode patterns, and the electrically conductive pattern is electrically connected to the ground electrode pattern, so that the electrically conductive pattern has a ground potential.
    Type: Application
    Filed: May 2, 2003
    Publication date: October 30, 2003
    Applicant: NEC COMPOUND SEMICONDUCTOR DEVICES, LTD.
    Inventor: Kouzi Hayasi
  • Patent number: 6639452
    Abstract: An active bias circuit having a combined configuration of the Wilson and Widlar current source configurations is provided, which makes it possible to set the output bias voltage at approximately zero (0V) even if a reference voltage applied to generate a reference current does not reach 0V. This circuit comprises cascode-connected first and second transistors, cascode-connected third and fourth transistors, and a resistor with a specific voltage drop generated by a current flowing through the same. The absolute value of the output bias voltage is decreased by the value of the voltage drop of the resistor compared with the case where the resistor is not provided. The resistor is provided between the gates/bases of the first and third transistors, or between the gate/base and source/emitter of the fourth transistor.
    Type: Grant
    Filed: December 16, 2002
    Date of Patent: October 28, 2003
    Assignee: NEC Compound Semiconductor Devices, Ltd.
    Inventors: Fuminobu Ono, Yoshikazu Nishimura
  • Patent number: 6640091
    Abstract: A transmission mixer (10) has a local input port (10LO) supplied with a local signal, an intermediate input port (10in) supplied with an input signal having an input frequency (fin) a first output port (10out1) for producing a first output signal having a first output frequency (fout1), and a second output port (10out2) for producing a second output signal having a second output frequency (fout2). The first and the second output ports (10out1, 10out2) are connected to first and second loads (LD1, LD2), respectively. The first load (LD1) is that where impedance-matching is made at the first output frequency (fout1) while the second load (LD2) is that where impedance-matching is made at the second output frequency (fout2).
    Type: Grant
    Filed: July 28, 2000
    Date of Patent: October 28, 2003
    Assignee: NEC Compound Semiconductor Devices, Ltd.
    Inventor: Osamu Shiraishi
  • Patent number: 6639453
    Abstract: An active bias circuit having a combined configuration of the Wilson and Widlar current source configurations is provided, which makes it possible to set the output bias voltage at approximately 0V even if a reference voltage applied to generate a reference current does not reach 0V. This circuit comprises cascode-connected first and second transistors, cascode-connected third and fourth transistors, and a diode with a specific forward voltage drop generated by a current flowing through the diode itself. The absolute value of the output bias voltage is decreased by the value of the forward voltage drop of the diode compared with the case where the diode is not provided. The diode is provided between the source/emitter of the third transistor and the drain/collector of the fourth transistor, or between the connection point of the third and fourth transistors and the output terminal, or the gates/bases of the first and third transistors.
    Type: Grant
    Filed: February 26, 2001
    Date of Patent: October 28, 2003
    Assignee: NEC Compound Semiconductor Devices, Ltd.
    Inventors: Yoshikazu Nishimura, Fuminobu Ono
  • Publication number: 20030197250
    Abstract: An electronic device includes (a) a first wiring substrate including a metal area and formed with a recess reaching the metal area, and (b) a second wiring substrate including a ground electrode formed in an area other than a signal transmission path at the recess and around the recess when coupled to the first wiring substrate, and further including at least one first electronic part mounted thereon. The first and second wiring substrates are coupled directly to each other such that the first electronic part is located in the recess.
    Type: Application
    Filed: April 22, 2003
    Publication date: October 23, 2003
    Applicant: NEC Compound Semiconductor Devices, Ltd.
    Inventors: Taibo Nakazawa, Koki Hirasawa
  • Patent number: 6627473
    Abstract: A high electron mobility transitor has a channel layer overlain by an electron supply layer held in contact with a gate electrode, and source/drain electrodes form ohmic contact together with cap layers, and resistive etching stopper are inserted between the cap layers and the electron supply layers for preventing the electron supply layer from over-etching, wherein extremely thin delta-doped layers are formed between the etching stopper layers and the electron supply layer so that the resistance between the electron supply layer and the source/drain electrodes are reduced.
    Type: Grant
    Filed: November 14, 2000
    Date of Patent: September 30, 2003
    Assignee: NEC Compound Semiconductor Devices, Ltd.
    Inventors: Hirokazu Oikawa, Hitoshi Negishi
  • Publication number: 20030169788
    Abstract: In a semiconductor laser diode module including a semiconductor laser diode having a front facet for emitting a light beam, a collimating lens for receiving the light beam to generate a collimated light beam and a coupling lens for receiving the collimated light beam and converging the collimated light beam to an optical fiber, a bandpass filter is provided for receiving a first part of the collimated light beam, and a light detector is provided to have a first portion for receiving the first part of the collimated light beam through the bandpass filter and a second portion for receiving a second part of the collimated light beam. Thus, a wavelength of the semiconductor laser diode is controlled in accordance with an output signal of the first portion of the light detector, and a light intensity of the semiconductor laser diode is controlled in accordance with an output signal of the second portion of the light detector.
    Type: Application
    Filed: March 3, 2003
    Publication date: September 11, 2003
    Applicant: NEC Compound Semiconductor Devices, Ltd.
    Inventor: Yoshitaka Yokoyama
  • Patent number: 6614311
    Abstract: A micro-wave power amplifier which amplifies a micro-wave signal including a plurality of carrier frequencies different from one another, includes (a) a field effect transistor having a grounded source, (b) a first difference frequency circuit which is electrically connected to a drain of the field effect transistor, and is short-circuited at a difference frequency between the carrier frequencies, and (c) a second difference frequency circuit which is electrically connected to a gate of the field effect transistor, and is short-circuited at a difference frequency between the carrier frequencies.
    Type: Grant
    Filed: November 29, 2001
    Date of Patent: September 2, 2003
    Assignee: NEC Compound Semiconductor Devices, Ltd.
    Inventor: Isao Takenaka
  • Publication number: 20030161109
    Abstract: An electronic product comprises a heat radiating plate, an electronic component securely mounted on the heat radiating plate and including a high power transistor, an enveloper including a frame member securely associated with the heat radiating plate to encompass the electronic component, and a lid member securely attached to an upper opening end of the frame member, thereby accommodating and sealing the electronic component in the enveloper, and at least one electrically conductive element passing and extending through the frame member. The frame member is made of a suitable resin material, and the lid member is made of one material selected from the group consisting of a ceramic material, a metal material, and a composite material.
    Type: Application
    Filed: February 25, 2003
    Publication date: August 28, 2003
    Applicant: NEC Compound Semiconductor Devices, Ltd.
    Inventors: Toshimichi Kurihara, Takashi Ueda
  • Publication number: 20030160249
    Abstract: An optical semiconductor device comprising a plurality of semiconductor lasers formed on a single substrate is provided, in which each of said semiconductor lasers emits a laser lights having designed different oscillating wavelength. This optical semiconductor device is provided by maintaining the coupling coefficient of each of said semiconductor lasers at a constant value by adjusting the composition of an optical guide layer or the mask width for the MOVPE growth.
    Type: Application
    Filed: February 25, 2003
    Publication date: August 28, 2003
    Applicant: NEC Compound Semiconductor Devices, Ltd.
    Inventor: Yasutaka Sakata
  • Publication number: 20030156604
    Abstract: A semiconductor laser to be produced by a method of the present invention includes a semiconductor substrate, a diffraction grating with an irregular surface formed on the semiconductor substrate, and an optical guide layer grown on the diffraction grating. A period of time over which the optical guide layer grows is selected such that the guide layer does not fill up the valleys of the diffraction grating. Also, the period of time remains substantially constant without regard to the variation of height of the diffraction grating.
    Type: Application
    Filed: February 19, 2003
    Publication date: August 21, 2003
    Applicant: NEC Compound Semiconductor Devices, Ltd.
    Inventor: Hiroyuki Yamazaki
  • Publication number: 20030136956
    Abstract: A heterojunction bipolar transistor has a raised breakdown voltage and restrains the rising characteristic of IC-VCE characteristic from degrading. The collector region includes first, second, and third collector layers of semiconductor. The first collector layer is made of a doped or undoped semiconductor in such a way as to contact the sub-collector region. The second collector layer is made of a doped or undoped semiconductor having a narrower band gap than the first collector layer in such a way as to contact the base region. The third collector layer has a higher doping concentration than the second collector layer in such a way as to be located between or sandwiched by the first collector layer and the second collector layer.
    Type: Application
    Filed: August 14, 2002
    Publication date: July 24, 2003
    Applicant: NEC Compound Semiconductor Devices, Ltd.
    Inventors: Takaki Niwa, Hidenori Shimawaki, Koji Azuma, Naoto Kurosawa
  • Publication number: 20030136967
    Abstract: A switching device for switching a plurality of RF signal lines to deliver a selected one of the RF signals to a receiver has an isolation D/U characteristic as high as 40 dB or higher. The switching device includes a mounting board made of dielectric and a matrix switch mounted thereon and implemented by one or more of SWIC. The RF signal lines in the switching device has no crossing point therebetween on either side of the mounting board to achieve the high isolation D/U ratio or lower cross-talk.
    Type: Application
    Filed: January 14, 2003
    Publication date: July 24, 2003
    Applicant: NEC Compound Semiconductor Devices, Ltd.
    Inventors: Toshio Suda, Hidenori Itoh
  • Patent number: 6593813
    Abstract: A negative feed-back amplifier is provided in which a distortion of signals is reduced and a dynamic range is increased. An input signal is input to a base of a transistor and is output from a collector as a reversed signal and a non-reversed signal is output from an emitter. The reversed signal is input to a base of a transistor and is output through a resistor from an emitter of the transistor. The non-reversed signal is input through a condenser to a base of a transistor and is output from a collector in a reversed form. An output signal from the transistor is input to an emitter follower of a transistor at high input impedance and output at low output impedance and then attenuated by resistors and negative feed-back signal is produced. The negative feed-back signal is input through a resistor to a base of the transistor to be added to the input signal.
    Type: Grant
    Filed: June 1, 2001
    Date of Patent: July 15, 2003
    Assignee: NEC Compound Semiconductor Devices, Ltd.
    Inventor: Tsuyoshi Matsushita
  • Publication number: 20030119233
    Abstract: A method of fabricating a semiconductor device is provided, which eliminates the possibility that the surface of a recess is contaminated before and after the process of forming a gate electrode, and which achieves sufficient controllability of the shape of a gate electrode. First and second dielectric layers, which have been formed successively to cover the recess of a semiconductor base material, are selectively removed by dry etching at approximately equal etch rates, thereby forming a gate opening that penetrates the second and first dielectric layers to reach the surface of the base material in the recess. A gate electrode with an approximately T-shaped cross section is formed to contact the surface of the base material in the recess by way of the gate opening. The second dielectric layer is selectively removed by wet etching at an etch rate sufficiently greater than an etch rate of the first dielectric layer, exposing the first dielectric layer.
    Type: Application
    Filed: December 17, 2002
    Publication date: June 26, 2003
    Applicant: NEC Compound Semiconductor Devices, Ltd.
    Inventor: Hirosada Koganei
  • Patent number: 6576178
    Abstract: An apparatus for sealing a resin uses a liquid resin. A substrate has a frame for surrounding the substrate and is provided with a plurality of semiconductor devices. The substrate has a first opening portion. A squeegee guide plate is placed on the frame and has a second opening portion. The second opening portion is larger than first opening portion in size. A first squeegee moves along the squeegee guide plate in a first direction and rakes the liquid resin. The liquid resin is protuberated in order to bury the semiconductor devices. A second squeegee moves along the squeegee guide plate in a second direction opposite to the first direction and further rakes the liquid resin so as to smooth a surface of the liquid resin. A turning mechanism serves to turn the second squeegee in a circular arc form during the movement of the second squeegee.
    Type: Grant
    Filed: December 21, 2000
    Date of Patent: June 10, 2003
    Assignee: NEC Compound Semiconductor Devices, Ltd.
    Inventors: Hideki Mizuno, Kiyomitsu Ishimura
  • Patent number: 6574258
    Abstract: A semiconductor laser, optical module using a semiconductor laser, and optical communication system using a semiconductor laser. The semiconductor laser has an active layer between two semiconductor layers and different conduction types and current block layers surrounding the active layer. One of the semiconductor layers has a first growth layer and a second growth layer formed on the first growth layer by a re-growth process after a growth process for the first growth layer. The doping concentration of the first growth layer, in the region of the interface with the second growth layer, is in the range of between 1.5 to 5 times the doping concentration of the second growth layer.
    Type: Grant
    Filed: January 23, 2001
    Date of Patent: June 3, 2003
    Assignee: NEC Compound Semiconductor Devices, Ltd.
    Inventor: Hiroyuki Yamazaki
  • Patent number: 6566185
    Abstract: A semiconductor device has a plurality of transistor units each of which is constituted by a unit prepared by arranging a plurality of unit cells each made up of a drain, gate, and source adjacent to each other on the major surface of a semiconductor substrate, a gate extraction electrode which extends in a direction perpendicular to the longitudinal direction of the gate and is commonly connected to the gates of the unit cells, a drain extraction electrode which is positioned at a side where the drain extraction electrode faces the gate extraction electrode via the unit, extends in a direction perpendicular to the longitudinal direction of the drain, and is commonly connected to the drains of the unit cells, a gate pad connected to the gate extraction electrode, and a drain pad connected to the drain extraction electrodes. The gate pads of adjacent transistor units are connected to each other by a gate extraction electrode connection wiring line having a resistor of 0.6 to 10 &OHgr;.
    Type: Grant
    Filed: October 11, 2001
    Date of Patent: May 20, 2003
    Assignee: NEC Compound Semiconductor Devices, Ltd.
    Inventors: Toshiaki Inoue, Toshirou Watanabe
  • Patent number: 6555763
    Abstract: A multilayered circuit board for a semiconductor chip module includes an underlying board, insulating layers, fixed-potential wiring layers, via holes, and metal layers. The underlying board has a major surface made of a metal material to which a fixed potential is applied. The insulating layers are stacked on the major surface of the underlying board and have wiring layers formed on their surfaces. The fixed-potential wiring layers constitute part of the wiring layers formed on the insulating layers. The via holes are formed below the fixed-potential wiring layers to extend through the insulating layers. The metal layers are filled in the via holes so as to make upper ends be connected to the lower surfaces of the fixed-potential wiring layers. One of the insulating layers in contact with the major surface of the underlying board is formed on the underlying board while the lower end of the metal layer is in contact with the major surface of the underlying board.
    Type: Grant
    Filed: September 15, 1999
    Date of Patent: April 29, 2003
    Assignees: Fuchigami Micro Co., Ltd., NEC Compound Semiconductor Devices Ltd.
    Inventors: Koki Hirasawa, Teruo Ono