Abstract: A data receiving device includes an elastic buffer which receives data as receiving data and adjusts timing with a sender, the data being scrambled and sent from the sender, an interpolation circuit which performs predetermined interpolation processing on the data subjected to timing adjustment by the elastic buffer to output the data, and a descramble circuit which descrambles the data output from the interpolation circuit. The receiving data includes data set for adjusting timing. The data set is for adjusting timing with the sender. The interpolation circuit replaces existing data with data for adjusting timing and outputs the data for adjusting timing as required after first receiving normal data for adjusting timing so that a desired number of data for adjusting timing is included in the data set for adjusting timing.

Abstract: A display device uses a plurality of pixel circuits each of which includes a light-emitting element; a light-emission control switching element; a current control circuit for supplying a driving current, which corresponds to gray-level display data, to the light-emitting element via the light-emission control switching element; and a voltage control circuit, which includes a first capacitance element for storing a voltage corresponding to the gray-level display data, and controls ON/OFF operation of the light-emission switching element in accordance with the voltage stored. If the gray-level display data is data for causing the light-emitting element to display less than a certain luminance, the current control circuit supplies the light-emitting element with a constant driving current corresponding to the gray-level display data for displaying the certain luminance, and the voltage control circuit controls the ON time of the light-emission control switching element in accordance with a voltage stored.

Abstract: Provided is a semiconductor device including: a first charge pump circuit that generates a first control signal based on electric charge of a first pumping capacitor accumulated through a first drive transistor; a second charge pump circuit that generates a second control signal based on electric charge of a second pumping capacitor accumulated through a second drive transistor; a third charge pump circuit that transfers electric charge between an output terminal and a reference voltage terminal through a third drive transistor; and a fourth charge pump circuit that transfers electric charge between the output terminal and the reference voltage terminal through a fourth drive transistor. Conductive states of the first and third drive transistors are controlled based on the second control signal, and conductive states of the second and fourth drive transistors are controlled based on the first control signal.

Abstract: An LPP detection unit detects an LPP from a wobble signal. A correction unit obtains a difference set by performing processing of calculating a difference in signal level between an LPP-present sync pattern portion and a non-LPP sync pattern portion having the same polarity, and executes correction on an RF signal at a timing when the LPP is detected, by using the difference set. The LPP-present sync pattern portion is a sync pattern portion obtained when the LPP is detected at the timing of the sync pattern portion positioned at the head of a sync frame of the RF signal. The non-LPP sync pattern portion is a sync pattern portion obtained when no LPP is detected at the timing of the sync pattern portion of the sync frame. In the case of reproducing information recorded on a DVD-R/RW optical disk, the occurrence of errors due to the effect of the LPP can be reduced.

Abstract: A heat sink 109 is configured by a plate component having a combined structure composed of a recess and a projection formed thereon, wherein the recess is formed by allowing a part of the plate component to be set back from the surface level of the residual region, and the projection is formed on one surface of the plate component with the progress of formation of the recess, so as to be built up above the level of the residual region of the one surface.

Abstract: A semiconductor integrated circuit, includes an operational amplifier including a first input terminal, a second input terminal, and an output terminal, a first transistor which has a source-drain route connected between an external terminal and a first voltage, and a gate terminal connected to the output terminal of the operational amplifier; and a second transistor which has a source-drain route connected between the first input terminal of the operational amplifier and the first voltage, and a gate terminal connected to the output terminal of the operational amplifier.

Abstract: A semiconductor device includes an electrode pad and an external connection terminal. The external connection terminal contains Sn equal to or more than 50 wt %, Sn and Pb equal to or more than 90 wt % in total, or Pb equal to or more than 85 wt %, and the surface thereof is coated with an Au layer. The thickness of the Au layer is preferably equal to or more than 10 nm and equal to or less than 1 ?m. The weight of the Au layer is preferably equal to or less than 0.6% of the weight of the external connection terminal.

Abstract: An input interface circuit according to the present invention includes an input first stage circuit that is connected to a signal terminal, where the signal terminal receives external data, and a phase adjustment circuit that adjusts an external input clock and a latch timing signal to be in phase, where the latch timing signal is output to latch circuits included in the input first stage circuit. The phase adjustment circuit adjusts delay time of the latch timing signal that passes through the clock tree circuit and is supplied to the latch circuit in response to a comparison result between the clock and an output from a replica delay circuit which is replicated from the clock.

Abstract: A method of fabricating a semiconductor device from a semiconductor wafer, having external connecting terminals on one side of the semiconductor wafer and a cover layer on another side of the semiconductor wafer, includes forming a groove with a first width from the one side to at least an interface between the semiconductor wafer and the cover layer in the semiconductor wafer, and cutting the cover layer with a second width from a bottom side of the groove. The second width is narrower than the first width.

Abstract: A die unit that maintains uniform quality of a work despite continuous operation is provided. The die unit includes a lower die holder including a base hole, an upper die holder including a through hole, a pillar having an end portion inserted to the base hole and the other end portion slidably inserted through the through hole, so as to allow the upper die holder to slide toward and away from the lower die holder, an annular bushing attached to the through hole so as to slide along the pillar, and a die element and a punch attached to one of the lower die holder and the upper die holder respectively. A spacer is provided at least one of between an inner circumferential surface of the through hole and the bushing, and between an inner circumferential surface of the base hole and the pillar, and the spacer has lower thermal conductivity than the upper die holder or the lower die holder on which the spacer is provided.

Abstract: A semiconductor device with integrated MIS field-effect transistors includes a first transistor including a first gate electrode having a composition represented by MAx, and a second transistor including a second gate electrode having a composition represented by MAy, in which M includes at least one metal element selected from the group consisting of W, Mo, Ni, Pt, Ta, Pd, Co, and Ti, A includes at least one of silicon and germanium, and 0<x?3, and 0<y?3, and x and y are different from each other.

Abstract: A multiplier PLL multiplies a reference clock and outputs the multiplied clock. A DLL compares the clock output from the multiplier PLL with a clock obtained by delaying the clock output from the multiplier PLL. The DLL generates a delay signal having a given amount of delay based on the comparison result. A delay control signal operation circuit generates a delay control signal based on the delay signal generated by the DLL. A first delay circuit delays an input signal based on the delay control signal generated by the delay control signal operation circuit.

Abstract: A semiconductor device includes a first circuit block powered by voltages at first and second power supply terminals, a second circuit block powered by voltages at third and fourth power supply terminals, a first ESD (electrostatic discharge) protection circuit including a first field effect transistor having a source, a drain, and a gate, where the gate and one of the source and the drain are connected to the first power supply terminal, the other of the source and the drain is connected to the third power supply terminal, and a first back gate potential adjusting circuit adapted to adjust a potential at a back gate of the first field effect transistor. The first field effect transistor includes a first conductivity type transistor formed in a first well of a second conductivity type serving as the back gate of the first field effect transistor.

Abstract: A light-receiving circuit includes a photodiode that converts an input optical signal to a current signal; a current-voltage converting circuit that outputs an output voltage signal obtained by adding a reference voltage to a voltage signal proportional to the current value of the current signal; and an input current limiting unit that supplies the current-voltage converting circuit with the current signal upon limiting the current value of this current signal based upon the reference voltage in such a manner that the output voltage signal will not exceed a constant value irrespective of the value of the reference voltage.

Abstract: Provided is that a lead-forming die includes an upper die and a lower die disposed so as to oppose the upper die; a supporting unit for semiconductor package, provided on an upper face of the lower die; a moving unit provided on a lower face of the upper die and movable in a direction that the upper die and the lower die oppose each other; a plurality of shafts supported by the moving unit so as to axially move with respect thereto; a presser provided above the supporting unit for semiconductor package, and at a lower end portion of the shaft; and a locking device that stops a movement of the shaft, provided between the upper die and the moving unit.

Abstract: An amplifier circuit includes an amplifier unit that amplifies a signal received by an input terminal and outputs the amplified signal to an output terminal, a feedback capacitor that is connected between the input terminal of the amplifier and the output terminal, and a controller that varies a capacitance in the feedback capacitor for a certain period when a potential of the output terminal in the amplifier unit becomes higher or lower than a certain potential.

Abstract: A D-A converter includes a resistor string that generates a plurality of voltages including an upper limit voltage, a lower limit voltage, and an intermediate voltage, a first selector that selects and outputs a first voltage among the plurality of voltages according to a lower bit, the first voltage being selected from the intermediate voltage and a voltage lower than the intermediate voltage, a second selector that selects and outputs a second voltage according to a higher bit, the second voltage being one of a lower power supply voltage and the intermediate voltage or a voltage higher than the intermediate voltage, a third selector that selects and outputs a third voltage according to the higher bit, the third voltage being selected from the lower limit voltage and the lower power supply voltage; and an amplifier that adds the first voltage and the second voltage and subtracts the third voltage.

Abstract: Provided is an analog-digital converter circuit having a normal mode for converting a received analog signal into a digital signal, and a calibration mode for adjusting an offset voltage of a comparator, the analog-digital converter including: a first comparator having a first analog signal input terminal supplied with an analog signal, and a first reference signal input terminal supplied with a first reference signal, in the normal mode; and a first calibration circuit that adjusts an offset voltage of the first comparator. In the calibration mode, assuming that a calibration resolution of the first calibration circuit is ?1, a potential difference between a reference signal supplied to the first analog signal input terminal and a reference signal supplied to the first reference signal input terminal is n1?1+?1/2 (where n1 is an integer).

Abstract: A method for manufacturing a semiconductor device includes forming a laminated structure of a plurality of metal films on a semiconductor substrate using an electroless plating method. The forming of the metal films includes: performing an electroless plating process including a reduction reaction using a first plating tank; and performing an electroless plating process by only a substitution reaction using a second plating tank. The electroless plating process including the reduction reaction that is performed using the first plating tank is performed in a shading environment, and the electroless plating process performed by only the substitution reaction using the second plating tank is performed in a non-shading environment.

Abstract: A semiconductor device includes a memory cell which includes a first inverter and a second inverter, the first inverter includes a first drive transistor and a first load transistor, the second inverter includes a second drive transistor and a second load transistor, and an input terminal and an output terminal thereof, respectively, connected to an input terminal and an output terminal of the first inverter, a first transmission transistor provided between the output terminal of the first inverter and a line of a first bit line pair, a second transmission transistor provided between the output terminal of the second inverter and another line of the first bit line pair, a third transmission transistor provided between the output terminal of the first inverter and a line of a second bit line pair, a fourth transmission transistor provided between the output terminal of the second inverter and another line of the second bit line pair, and a first isolation transistor which isolates the second drive transistor a