Abstract: A charge pump circuit, whose output is connected to a first node, starts a boosting operation after start of a test period. A load current application circuit supplies a load current to the first node during the test period. A voltage of the first node is a write voltage. A memory circuit stops application of the write voltage to a memory cell during the test period, and applies the write voltage to the memory cell after end of the test period. A high voltage detection unit compares the write voltage and a predetermined voltage to determine whether or not the write voltage is increased to the predetermined voltage. If the write voltage is less than the predetermined voltage at the end of the test period, the high voltage detection unit activates a disable signal. If the disable signal is activated, the charge pump circuit stops the boosting operation.

Abstract: In a soldering method for mounting a semiconductor device on a wiring board, a plurality of solid-phase solders are provided between the semiconductor device and the wiring board, and are thermally melted to thereby produce a plurality of liquid-phase solders therebetween. A constant force is exerted on the liquid-phase solders by relatively moving the semiconductor device with respect to the wiring board so that an invariable gap is determined between the semiconductor device and the wiring board.

Abstract: Method of cleaning a plasma etching apparatus capable of suppressing variation in line width among wafers in a single lot, and improving throughput in the cleaning process, includes steps of supplying a cleaning gas into a chamber of a plasma etching apparatus; igniting a plasma of the cleaning gas in the chamber; and allowing plasma cleaning to proceed in the chamber, by bringing the cleaning gas in plasma form into contact with a deposit adhered on the inner wall of the chamber so as to etch off the deposit, wherein in the step of plasma cleaning in the chamber, intensity of plasma emission ascribable to the deposit adhered on the inner wall of the chamber is detected in a time-dependent manner, and the plasma cleaning in the chamber is terminated based on changes in the intensity of the plasma emission.

Abstract: A compressed stream decoding apparatus to preventing a disturbance of a display image is disclosed. The compressed stream decoding apparatus includes: a first video data processor decoding an input first compressed video stream based on first reference time information added to the first compressed video stream, and outputting decoded video data based on the first reference time information; and a second video data processor performing alternatively a first processing and a second processing, wherein the first processing is decoding an input second compressed video stream based on second reference time information added to the second compressed video stream and outputting decoded video data based on the second reference time information; and the second processing is outputting the decoded video data decoded by the first video data processor based on the first reference time information.

Abstract: A first exemplary aspect of the present invention is an image processing device that executes image processing including first image processing and second image processing by using a pipeline mechanism, the image processing device including: a first processing unit that executes the first image processing on an input image data, generates history information recording specifics of processing executed in the first image processing, and outputs the history information to the first processing unit; and a second processing unit that executes the second image processing on the image data obtained in the first image processing according to the output history information.

Abstract: A semiconductor integrated circuit includes a first circuit, a second circuit and a control circuit. The first circuit is configured by a first MOS transistor, and a threshold voltage of the first MOS transistor is a first threshold voltage. The second circuit has same logic as the first circuit, and is configured by a second MOS transistor. A threshold voltage of the second MOS transistor is a second threshold voltage, and the second threshold voltage is lower than the first threshold voltage. The control circuit makes one of the first circuit and the second circuit operate depending on a temperature of a chip. The first circuit and the second circuit are installed in a chip.

Abstract: One exemplary embodiment includes a semiconductor chip that has a rectangle principal surface including a first and a second side that oppose each other. A first and a second semiconductor element, and a first and a second wire are formed on the principal surface. The first wire is formed from the first side to reach the second side, and coupled to the first semiconductor element. The second wire is formed to contact at least the first wire, and coupled to the second semiconductor element. Further, an edge part of the first wire on the second side and an edge part of the second wire on the first side are placed to substantially position on a common straight line which is vertical to the first and the second sides.

Abstract: The manufacturing method includes: forming a seed film on a semiconductor chip; forming a photoresist having an opening above an electrode of the semiconductor chip on the seed film; forming a first Au bump on the seed film in the opening by electrolytic plating with a current density of 1.5 A/dm2 or above; grinding a surface of the first Au bump; stripping the photoresist; and removing the seed film by dry-etching.

Abstract: A semiconductor device includes: a noise detecting circuit; an input signal delaying circuit; and a mask circuit. The noise detecting circuit detects noise superimposed on an input signal and outputs a mask signal during a predetermined time period. The input signal delaying circuit delays the input signal and outputs a delay signal thereof. The mask circuit outputs an output signal in which the delay signal is masked based on the mask signal.

Abstract: A method of manufacturing a semiconductor device includes forming a barrier metal film including a high melting point metal in a concave portion formed in an insulating film formed over a substrate; forming a seed alloy film including copper and an impurity metal different from the copper over the barrier metal film so as to fill a portion of the concave portion; forming a plated metal film containing copper as a major ingredient over the seed alloy film so as to fill the concave portion; first heat-treating the seed alloy film and the plated metal film at 200° C. or higher and for ten minutes or less; removing the plated metal film, the seed alloy film, and the barrier metal film which are exposed to the outside of the concave portion, after the first heat-treating; and second heat-treating the seed alloy film and the plated metal film.

Abstract: A semiconductor device includes a wiring layer, a semiconductor chip which is arranged on the wiring layer with a gap there between, the semiconductor chip being electrically connected to the wiring layer through a connecting portion, a first sealing member which is filled in a space between the wiring layer and the semiconductor chip, and a second sealing member which coats the semiconductor chip. The first sealing member and the second sealing member include same organic resin, the organic resin including inorganic filler. The second sealing member has larger content of inorganic filler than the first sealing member.

Abstract: A reliability reference storage unit stores reference data for dividing semiconductor devices into equal to or more than three reliability ranks on the basis of the magnitude of an overlay error between a first interconnect layer and a second interconnect layer disposed over the first interconnect layer. An error storage unit stores overlay errors measured at multiple points within the surface of a semiconductor wafer. An error calculation unit calculates the overlay errors for a plurality of semiconductor chips on the basis of the coordinates of the plurality of semiconductor chips within the surface of the semiconductor wafer and the overlay errors stored in the error storage unit. A reliability information providing unit provides reliability information indicating reliability ranks to the plurality of semiconductor chips on the basis of the overlay errors for the plurality of semiconductor chips and reference data.

Abstract: A microcomputer includes a CPU, a standby controller that controls setting of and recovering from a sleep mode of the CPU, an output terminal, a first timer, an output terminal controller, and a second timer. When the first timer performs predetermined time measurement when the CPU is in the sleep mode, the output terminal controller changes the level of the output terminal while maintaining the sleep mode. The second timer starts time measurement when the output terminal controller changes the level of the output terminal in the sleep mode. The standby controller performs recovering from the sleep mode of the CPU when the second timer performs a prescribed time measurement.

Abstract: A semiconductor device, includes a first wiring pattern in a first region, a second wiring pattern in a second region, and at least one first dummy pattern formed in the first region and at least one second dummy pattern formed in the second region. A total area of the at least one first dummy pattern is the same as a total area of the at least one second dummy pattern and a total length of pattern periphery of the at least one second dummy pattern is longer than a total length of pattern periphery of the at least one first dummy pattern.

Abstract: In a method of performing a test on a logic circuit in accordance with an exemplary aspect of the present invention, the test is performed by supplying a clock signal from a clock supply circuit to a plurality of clock domains operating by a clock signal of a same frequency. The method includes calculating a number of test patterns of each of the plurality of internal clock domains; classifying the plurality of clock domains into a plurality of groups based on the calculated number of test patterns; and assigning a clock supply circuit independently to each of the groups into which the clock domains are classified.

Abstract: A driver circuit according to the present invention includes a grayscale circuit, an amplifier circuit, a comparison circuit, and a sampling timing adjusting circuit. The grayscale circuit generates a grayscale voltage from grayscale data. The amplifier circuit generates a video output from the grayscale voltage. The comparison circuit compares the grayscale voltage with the video output and outputs a comparison result. The sampling timing adjusting circuit adjusts a sampling timing signal for sampling the video signal based on the comparison result to generate an adjusted sampling timing signal.

Abstract: A first adjusting metal, capable of varying the threshold voltage of a first-conductivity-type transistor of a complementary transistor, is added to the first-conductivity-type transistor and a second-conductivity-type transistor at the same time, and a diffusion suppressive element, capable of suppressing diffusion of the first adjusting metal, is added from above a metal gate electrode of the second-conductivity-type transistor.

Abstract: Provided is a semiconductor apparatus including a divided voltage generation circuit that includes a first resistor element and a first transistor connected in series between a first power supply and a second power supply and generates a divided voltage by dividing a voltage difference between the first power supply and the second power supply with a resistance ratio of the first resistor element and the first transistor specified according to a level of a first current flowing to the first transistor, and a current control circuit that includes a second transistor that is connected in a mirror configuration to the first transistor and determines the level of the first current by a control current flowing from a first terminal to a second terminal, and increases and decreases the control current according to an increase and decrease in a voltage difference between the first power supply and a ground power supply.

Abstract: In a semiconductor integrated circuit device, a shift register includes a plurality of cascaded flip-flops adapted to generate shift pulse signals in response to a start signal. A logic circuit receives a pulse signal at its input end and supplies the pulse signal from its plurality of output ends to the flip-flops. The pulse signal at each of the plurality of output ends is allowed and prohibited by a corresponding one of the shift pulse signals.

Abstract: A receiving circuit which receives information using a multi-carrier signal comprises a phase rotation amount calculator which calculates a phase rotation amount of a multi-carrier signal included in a first frequency band according to a pilot-sub carrier included in the first frequency band, a converter which calculates a phase rotation amount of a multi-carrier signal included in a second frequency band according to the phase rotation amount of the multi carrier signal included in the first frequency band.