Abstract: In a technique connecting between bonding pads of semiconductor chips, contact between wires is prevented. A semiconductor device of the present embodiment is provided with a semiconductor chip 1 in which a plurality of bonding pads 3 are arranged in line, a semiconductor chip 2 in which a plurality of bonding pads 4 are arranged in line substantially parallel to the plurality of bonding pads 3, and a plurality of wires 7 which connect the bonding pads 3 to the bonding pads 4 respectively. At least one of the wires 7 is bended with respect to a reference straight line S which passes through the bonding pad 3 and the bonding pad 4 which are connected by the wire 7. The bended wire is extended out from the bonding pad 4 in a certain direction in which a distance between the bended wire and an adjacent wire which is adjacent to the bended wire is larger than a distance between the reference straight line of the bended wire and the reference straight line of the adjacent wire.

Abstract: A semiconductor device (100) includes a semiconductor substrate (2), an inductor (4) provided on the semiconductor substrate (2), a metal ball (8) provided on the inductor (4) so as to come into contact with the inductor (4), and a bonding wire (10) electrically connected to the metal ball (8). The semiconductor device (100) exchanges signals with an external via the inductor (4) and the metal ball (8). The inductor (4) also serves as the bonding pad and therefore the inductor and the bonding pad need not to be arranged in pairs.

Abstract: A semiconductor device is provided including a first fuse link having a copper-containing metal film, a second fuse link having a polysilicon film, a semiconductor substrate, and a field insulating film formed on the semiconductor substrate. The second fuse link is formed on the field insulating film. An interlayer insulating film is provided between the first fuse link and the second fuse link. The first fuse link is electrically connected to the second fuse link via a first plug formed in the interlayer insulating film.

Abstract: A nonvolatile semiconductor memory device has: a semiconductor substrate; a control gate and a floating gate that are formed side by side on a gate insulating film on a channel region in the semiconductor substrate; an erase gate facing an upper surface of the floating gate; a first device isolation structure having a first projecting portion; and a second device isolation structure having a second projecting portion. The first and second projecting portions have a first sloping surface and a second sloping surface, respectively. The first sloping surface and the second sloping surface face each other, and an interval between the first and second sloping surfaces becomes larger away from the semiconductor substrate. The floating gate is sandwiched between the first and second projecting portions and at least has a portion located on the semiconductor substrate side of the first and second sloping surfaces.

Abstract: Between a control terminal (gate) of an output transistor of a source follower configuration and an output terminal to which a load is coupled, a depletion transistor having a relatively lower breakdown voltage (that is, smaller device-area) is provided as a shutdown transistor of the output transistor, to thereby control a conductive state/nonconductive state of the depletion transistor. There are provided: the output transistor of the source follower configuration coupled between a first power supply line and the output terminal; the load coupled between the output terminal and a second power supply line; the depletion transistor coupled between the gate of the output transistor and the output terminal; and a control circuit controlling the conductive state/nonconductive state of the depletion transistor by applying, between a gate and a source thereof, a voltage smaller than a voltage deference between a potential of the first power supply line and a potential of the second power supply line.

Abstract: An encoding device includes a buffer for performing EDC generation, scrambling and ECC generation on user data arranged along user data direction Q that is read out from a data buffer of SDRAM and storing the operation results, a substitution buffer for repeatedly reading out the user data by burst transfer from the data buffer and outputting the data in recording frame direction P, and a scrambler for scrambling the data output from the substitution buffer along the direction P according to the operation results and outputting scrambled data. The substitution buffer is configured by SRAM and has a memory capacity of equal to or larger than a minimum capacity to output user data in the direction P and smaller than a memory capacity of the data buffer.

Abstract: A semiconductor apparatus includes a semiconductor device formed to a first surface of a semiconductor substrate, a blocking film provided in a first via-hole, the first via-hole formed with a concave shape to the first surface of the semiconductor substrate, a first via line connected to an electrode of the semiconductor device in contact with the blocking film, a second via line formed inside a second via-hole, electrically connected with the first via line with the blocking film interposed therebetween and being apart of a wiring formed to a second surface, the second via-hole formed with a concave shape to the second surface opposing the first surface of the semiconductor substrate so as to reach the blocking film. The blocking film includes at least one kind of group 8 element.

Abstract: In a method of manufacturing a semiconductor device where at least one insulating layer structure having a metal wiring constitution is formed to thereby construct a multi-layered wiring arrangement, a first SiOCH layer is produced. Then, a surface section of the first SiOCH layer is treated to change the surface section of the first SiOCH layer to a second SiOCH layer which features a carbon (C) density lower than that of the first SiOCH layer, a hydrogen (H) density lower than that of the first SiOCH layer and an oxygen (O) density higher than that of the first SiOCH layer. Finally, a silicon dioxide (SiO2) layer is formed on the second SiOCH layer.

Abstract: An overvoltage protection circuit includes a PMOS transistor Q1 that is disposed between an input circuit 21, from which an input voltage VIN is supplied, and a system 22 and functions as a switch. A comparator 110 compares the input voltage VIN with a predetermined reference voltage to determine the occurrence of an overvoltage. Further, the comparator 110 outputs a High level as an operation signal when no overvoltage is detected. A soft switching control circuit 130 starts up by using the High level output from the comparator 110 as an enable signal, and gradually turns on the PMOS transistor Q1. A sudden change of the load exerted on the circuit on the input side is suppressed by the soft start function.

Abstract: A semiconductor chip includes a plurality of pads, input circuits or output circuits that are electrically connected to the pads, a main control unit that outputs a read access signal, the read access signal controlling reading of signals from an external circuit or an internal circuit, and activation control units that control activation of the input circuits or the output circuits that are electrically connected to the pads based on the read access signal, the pads receiving the signals from the external circuit or the internal circuit.

Abstract: A memory checking system according to the present invention includes a memory that stores a data to be checked, a check circuit that checks the memory by using the data to be checked and a reference check code of the data to be checked, and a transfer circuit that transfers the data to be checked from the memory to the check circuit based on a transfer setting information of the data to be checked. The transfer setting information is registered in advance in the memory.

Abstract: An A/D conversion circuit includes a plurality of transmission paths that transmit signal voltages and reference voltages, and an A/D conversion unit that A/D converts voltages output from the transmission paths. Each of the plurality of transmission paths includes a first switch that selectively outputs one of the signal voltage and the reference voltage, an S/H circuit that holds output voltage from the first switch, and a second switch that selectively outputs one of the output voltage from the first switch and output voltage from the S/H circuit.

Abstract: A semiconductor apparatus with a superjunction structure includes a gate electrode which fills a trench that is formed in an epitaxial layer, and a column region which is surrounded by the gate electrode in a plane view. A photomask for forming the column region is elaborated. The photomask has a compensation pattern that compensates a deformation of a photo resist pattern caused by photo interference and a deformation of the ion implantation region diffused by heat treatment. Therefore extending direction of the gate electrode and the outer edge of the column region are substantially parallel.

Abstract: A semiconductor memory device includes a control circuit to control an access to a memory cell according to an input command, a transfer mode setting circuit to hold a transfer mode, an address pin input/output with an address in a first transfer mode and input/output with data in a second transfer mode and a switching circuit to switch a connection destination of the address.

Abstract: A differential amplifier circuit 110 composed of an inverter is connected to the power supply voltage VCC and the ground voltage GND through a NMOS transistor 142 and a PMOS transistor 144 respectively. The NMOS transistor 142 is connected to the control signal terminal PS, and the PMOS transistor 144 is connected to control signal terminal PS through an inverter 150. The NMOS transistor 142 and the PMOS transistor 144 are controlled such that they can be simultaneously cut off by a control signal from the control signal terminal PS. In this way, the power consumption of the amplifier is reduced.

Abstract: In a laser beam processing apparatus that processes a semiconductor wafer having a multi-layered wiring structure formed thereon, scribe lines defined thereon, and at least one alignment mark formed on any one of the scribe lines, a laser beam generator system generates a laser beam, and a movement system relatively moves the semiconductor wafer with respect to the laser beam such that the semiconductor wafer is irradiated with a laser beam along the scribe lines to partially remove the multi-layered wiring structure from the semiconductor wafer along the scribe lines. An irradiation control system controls the irradiation of the semiconductor wafer with the laser beam along the scribe lines such that the alignment mark is left on the scribe line.

Abstract: An output buffer circuit constituted by a totem-pole circuit where two NchMOS transistors are cascade-connected, and the connection point of the two MOS transistors are connected to a data electrode of a display cell, improves the power recovery rate of a driver device of a PDP. A level shift circuit includes a CMOS circuit and drives the output buffer circuit. An electric charge recovery circuit connected to a power supply of the output buffer circuit recovers and reuses electric charges remaining on the data electrode after the discharge of the display cells. A power supply control circuit controls so that the power supply voltage of the level shift circuit is higher than the sum of the power supply voltage of the output buffer circuit and the threshold voltage of the MOS transistors for a period of time during a recovery/reuse cycle of the electric charge recovery circuit.

Abstract: In a conventional semiconductor device, an excessive etching occurs in a section where an opening for contact plug is formed, causing a damage to a diffusion layer located under the opening. A semiconductor device 1 includes a region D1 for forming an electric circuit, and a seal ring 30 (guard ring) that surrounds the region D1 for forming the electric circuit. A DRAM 40 is formed in the region D1 for forming the electric circuit. Interlayer insulating films 22, 24, 26 and 28 are formed on a semiconductor substrate 10. The seal ring 30 is formed in the interlayer insulating films 22, 24, 26 and 28, and at least a portion there of is located spaced apart from the semiconductor substrate 10.

Abstract: In a semiconductor integrated circuit design method for carrying out a design of circuit patterns, a plurality of circuit patterns are defined, and each of the circuit patterns is composed of at least one minimum unit area. One of the circuit patterns is selected, and an expansion area is defined with respect to the selected circuit pattern so that the selected circuit pattern is at least included in the expansion area. An area ratio of an area size of the circuit pattern or circuit patterns included in the expansion area to an area size of the expansion area is calculated, and the area ratio is compared with a reference value.

Abstract: Formation of a constricted portion in an interconnect pattern is inhibited while moderating design rule for a phase shifting mask.